Abstract: A thin film transistor including a substrate, a semiconductor layer, a patterned doped semiconductor layer, a source and a drain, a gate insulation layer, and a gate is provided. The semiconductor layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on opposite sides of the semiconductor layer. The source and the drain are disposed on the patterned doped semiconductor layer and the opposite sides of the semiconductor layer, wherein a part of the semiconductor layer covered by the source and the drain has a first thickness, a part of the semiconductor layer disposed between the source and the drain and not covered by the source and the drain has a second thickness ranging from 200 ? to 800 ?. The gate insulation layer is disposed on the source, the drain and the semiconductor layer. The gate is disposed on the gate insulation layer.

Abstract: A thin film transistor including a substrate, a semiconductor layer, a patterned doped semiconductor layer, a source and a drain, a gate insulation layer, and a gate is provided. The semiconductor layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on opposite sides of the semiconductor layer. The source and the drain are disposed on the patterned doped semiconductor layer and the opposite sides of the semiconductor layer, wherein a part of the semiconductor layer covered by the source and the drain has a first thickness, a part of the semiconductor layer disposed between the source and the drain and not covered by the source and the drain has a second thickness ranging from 200 ? to 800 ?. The gate insulation layer is disposed on the source, the drain and the semiconductor layer. The gate is disposed on the gate insulation layer.

Abstract: A thin film transistor including a substrate, a semiconductor layer, a patterned doped semiconductor layer, a source and a drain, a gate insulation layer, and a gate is provided. The semiconductor layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on opposite sides of the semiconductor layer. The source and the drain are disposed on the patterned doped semiconductor layer and the opposite sides of the semiconductor layer, wherein a part of the semiconductor layer covered by the source and the drain has a first thickness, a part of the semiconductor layer disposed between the source and the drain and not covered by the source and the drain has a second thickness ranging from 200 ? to 800 ?. The gate insulation layer is disposed on the source, the drain and the semiconductor layer. The gate is disposed on the gate insulation layer.

Abstract: A fabricating method of an organic electroluminescent display unit is provided. A gate and a gate insulating layer covering the gate are formed on the substrate. A patterned metal-oxide layer with an etching stop layer thereon is formed on the gate insulating layer. A surface treatment is performed on the patterned metal-oxide layer with use of the etching stop layer as a mask, such that a portion of the patterned metal-oxide layer uncovered by the etching stop layer has greater conductivity than conductivity of another portion of the patterned metal-oxide layer covered by the etching stop layer. The patterned metal-oxide layer treated by the surface treatment includes a pixel electrode and an active layer located above the gate. A source and a drain are then formed. And then, an organic electro-luminescence layer and a top electrode are sequentially formed on the pixel electrode.

Abstract: A fabricating method of an organic electroluminescent display unit is provided. A gate and a gate insulating layer covering the gate are formed on the substrate. A patterned metal-oxide layer with an etching stop layer thereon is formed on the gate insulating layer. A surface treatment is performed on the patterned metal-oxide layer with use of the etching stop layer as a mask, such that a portion of the patterned metal-oxide layer uncovered by the etching stop layer has greater conductivity than conductivity of another portion of the patterned metal-oxide layer covered by the etching stop layer. The patterned metal-oxide layer treated by the surface treatment includes a pixel electrode and an active layer located above the gate. A source and a drain are then formed. And then, an organic electro-luminescence layer and a top electrode are sequentially formed on the pixel electrode.

Abstract: A pixel structure is disposed on a substrate and includes a gate, a gate insulating layer, a patterned metal-oxide layer, an etching stop layer, a source, and a drain. The gate is disposed on the substrate. The gate insulating layer is disposed on the substrate to cover the gate. The patterned metal-oxide layer is disposed on the gate insulating layer and includes an active layer located above the gate and a pixel electrode. The etching stop layer is disposed on a portion of the active layer. Conductivity of a portion of the patterned metal-oxide layer uncovered by the etching stop layer is greater than conductivity of a portion of the patterned metal-oxide layer covered by the etching stop layer. The source and the drain are electrically connected to a portion of the active layer uncovered by the etching stop layer. The drain is electrically connected to the pixel electrode.

Abstract: A thin film transistor including a substrate, a semiconductor layer, a patterned doped semiconductor layer, a source and a drain, a gate insulation layer, and a gate is provided. The semiconductor layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on opposite sides of the semiconductor layer. The source and the drain are disposed on the patterned doped semiconductor layer and the opposite sides of the semiconductor layer, wherein a part of the semiconductor layer covered by the source and the drain has a first thickness, a part of the semiconductor layer disposed between the source and the drain and not covered by the source and the drain has a second thickness ranging from 200 ? to 800 ?. The gate insulation layer is disposed on the source, the drain and the semiconductor layer. The gate is disposed on the gate insulation layer.

Abstract: A pixel structure is disposed on a substrate and includes a gate, a gate insulating layer, a patterned metal-oxide layer, an etching stop layer, a source, and a drain. The gate is disposed on the substrate. The gate insulating layer is disposed on the substrate to cover the gate. The patterned metal-oxide layer is disposed on the gate insulating layer and includes an active layer located above the gate and a pixel electrode. The etching stop layer is disposed on a portion of the active layer. Conductivity of a portion of the patterned metal-oxide layer uncovered by the etching stop layer is greater than conductivity of a portion of the patterned metal-oxide layer covered by the etching stop layer. The source and the drain are electrically connected to a portion of the active layer uncovered by the etching stop layer. The drain is electrically connected to the pixel electrode.