Abstract: In accordance with the present invention, a metal oxide semiconductor (MOS) transistor has a substrate of a first conductivity type. A drift region of a second conductivity type extends over the substrate. A body region of the first conductivity type is in the drift region. A source region of the second conductivity is in the body region. A gate extends over a surface portion of the body region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor. A drain region of the second conductivity type is in the drift region. The drain region is laterally spaced from the body region. A first buried layer of the second conductivity type is between the substrate and drift region. The first buried layer laterally extends from under the body region to under the drain region. A second buried layer of the first conductivity type is between the first buried layer and the drift region.

Abstract: In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

Abstract: A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof. The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.

Abstract: A trench DMOS device having improved breakdown characteristics. The trench DMOS device has a gate oxide layer which has a substantially flattened thick portion in the bottom of the trench and which is relatively thinner on the sidewalls. In greater detail, the trench DMOS device comprises a trench formed in a semiconductor substrate, said trench having sidewalls and a bottom, a gate polysilicon layer filled into said trench, and a gate oxide layer formed between said gate polysilicon layer and the sidewalls and bottom of said trench, wherein a bottom part of said gate oxide layer has a thickness greater than both sidewall parts thereof, and a central region of said bottom part is substantially flattened with a thickness greater than boundary regions thereof. Also disclosed is a novel method of fabricating a trench DMOS device.

Abstract: A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.

Abstract: A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed.

Abstract: A high voltage semiconductor device having a high breakdown voltage isolation region, in which the high breakdown voltage isolation region and a junction termination including a lateral DMOS transistor are formed between a high voltage region and a low voltage region. The lateral DMOS transistor and the high breakdown voltage isolation region are formed on a structure in which a semiconductor substrate of a first conductivity type and an epitaxial layer of a second conductivity type are sequentially formed. The epitaxial layers in the high breakdown voltage isolation region, the lateral DMOS transistor and the high voltage region are isolated from each other by first diffusion regions of a first conductivity type, which are formed between a certain depth of the semiconductor substrate and a certain depth of the epitaxial layer.

Abstract: A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed.

Abstract: In a DMOS field effect transistor according to the present invention, a drift region of a first conductivity type is formed on a semiconductor substrate. A gate electrode is formed over the drift region, interposing a gate insulating layer between the drift region and the gate electrode. The gate electrode includes a gate conductive layer and a conductive spacer formed on the side wall of the gate conductive layer. A body region is formed to be self-aligned by the gate conductive layer. The source region is formed to be self-aligned by the conductive spacer. Therefore, a doping profile in a channel region of the body region has a form in which a uniform doping density value is maintained. Therefore, although the threshold voltage of the device is lowered by reducing the peak doping density, the density of impurities in the channel region is not decreased. Therefore, a punch-through characteristic is not deteriorated.

Abstract: A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate and isolation trenches are formed at both sides of the well region. A high density second conductive type buried layer is formed in the semiconductor substrate which is formed at the bottom of the isolation trench. The buried layer is formed in two regions surrounding respective bottoms of two adjacent isolation trenches. The two regions are electrically connected with each other and in direct contact with the well region. An extrinsic base region and a device isolation region are formed sequentially onto the semiconductor substrate using a nitration layer pattern as a mask, wherein the nitration layer pattern is formed on the surface of semiconductor substrate.

Abstract: Semiconductor-on-insulator (SOI) devices are fabricated by forming first and second semiconductor layers of opposite conductivity types, at a first face of a substrate. An insulating layer is formed on the first and second semiconductor layers. A trench is formed through the insulating layer extending between the first and second semiconductor layers and extending into the substrate. A portion of the substrate is removed from a second face which is opposite the first face, to define respective first and second active regions on the respective first and second semiconductor layers.

Abstract: A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate and isolation trenches are formed at both sides of the well region. A high density second conductive type buried layer is formed in the semiconductor substrate which is formed at the bottom of the isolation trench. The buried layer is formed in two regions surrounding respective bottoms of two adjacent isolation trenches. The two regions are electrically connected with each other and in direct contact with the well region. An extrinsic base region and a device isolation region are formed sequentially onto the semiconductor substrate using a nitration layer pattern as a mask, wherein the nitration layer pattern is formed on the surface of semiconductor substrate.

Abstract: Methods of forming vertical trench-gate semiconductor devices include the steps of patterning an oxidation resistant layer having an opening therein, on a face of a semiconductor substrate, and then forming a trench in the semiconductor substrate, opposite the opening in the oxidation resistant layer. An insulated gate electrode is then formed in the trench. The face of the semiconductor substrate is then oxidized to define self-aligned electrically insulating regions in the opening and at a periphery of the patterned oxidation resistant layer. Here, the patterned oxidation resistant layer is used as an oxidation mask so that portions of the substrate underlying the oxidation resistant layer are not substantially oxidized. Source and body region dopants of first and second conductivity type, respectively, are then implanted into the substrate to define preliminary source and body regions which extend adjacent a sidewall of the trench.

Abstract: A semiconductor device, and a method of manufacturing the same, containing a high voltage DMOS transistor, a low voltage CMOS transistor, and a bipolar transistor in a single substrate. The steps include forming an isolation layer within the substrate in an isolation region between each of a DMOS region, a CMOS region, or a bipolar region. A first oxide layer of variable thickness is formed on the substrate, a thick second oxide layer is formed on the isolation layer, and a polysilicon layer is formed on both oxide layers. The polysilicon layer is patterned to form gate patterns on the first oxide layer and resistive patterns on the second oxide layer. The gate pattern is then doped but the resistive pattern is undoped. The thickness of the first oxide layer in the DMOS region is greater than the thickness of the first oxide layer in the CMOS region.

Abstract: An insulated gate power semiconductor device includes an array of base contact openings in a continuous source region at a face of a semiconductor substrate, and an array of trenches therein. The trenches are preferably interspersed among the array of base contact openings to maximize the effective channel width of the inversion layer channels which are formed in a base region during forward conduction. The device contains a drift region of first conductivity type therein as well as a base region of second conductivity type which extends between the drift region and the first face. In addition, a continuous source region of first conductivity type is provided which extends from the base region to the first face. The source region also has a two-dimensional array of base contact openings therein through which the base region extends.