Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: A duty correction device includes a clock generation circuit, first and second correction pulse generation circuits, and a duty correction circuit. The clock generation circuit generates first to third divided clock signals, each having a phase offset from a reference clock signal. The first correction pulse generation circuit generates a first correction pulse by detecting a phase difference between a delayed clock signal and the first and second divided clock signals. The second correction pulse generation circuit generates a second correction pulse by detecting a phase difference between the second and third divided clock signals. The duty correction circuit checks whether the first and second correction pulses are generated at a preset logic level of the reference clock signal, and reflects the first or second correction pulses in a duty correction operation for the reference clock signal according to a result of the check.

Abstract: A stacked integrated circuit includes a first chip including a first through via set and a second through via set that are disposed to be symmetrical to each other in relation to a first rotating axis and including a first input and output (IO) circuit and a second IO circuit that are disposed to be asymmetrical to each other in relation to the first rotating axis and a second chip including a third through via set and a fourth through via set that are disposed to be symmetrical to each other in relation to a second rotating axis and including a third IO circuit and a fourth IO circuit that are disposed to be asymmetrical to each other in relation to the second rotating axis, the second chip being rotated around the second rotating axis and stacked on the first chip.

Abstract: An integrated circuit (IC) chip includes a plurality of interlayer channels; at least one data pad; an identification (ID) generation circuit suitable for generating a chip ID signal by decoding a command/address signal; a first transmission circuit suitable for transferring a plurality of internal data pieces to a transmission path by aligning a plurality of interlayer data pieces respectively transferred from the plurality of interlayer channels according to a plurality of strobe signals while selectively inverting the plurality of interlayer data pieces according to the chip ID signal; and a second transmission circuit suitable for transferring the plurality of internal data pieces from the transmission path to the at least one data pad.

Abstract: An integrated circuit (IC) chip includes a plurality of interlayer channels; at least one data pad; an identification (ID) generation circuit suitable for generating a chip ID signal by decoding a command/address signal; a first transmission circuit suitable for transferring a plurality of internal data pieces to a transmission path by aligning a plurality of interlayer data pieces respectively transferred from the plurality of interlayer channels according to a plurality of strobe signals while selectively inverting the plurality of interlayer data pieces according to the chip ID signal; and a second transmission circuit suitable for transferring the plurality of internal data pieces from the transmission path to the at least one data pad.

Abstract: A duty correction device includes a clock generation circuit, first and second correction pulse generation circuits, and a duty correction circuit. The clock generation circuit generates first to third divided clock signals, each having a phase offset from a reference clock signal. The first correction pulse generation circuit generates a first correction pulse by detecting a phase difference between a delayed clock signal and the first and second divided clock signals. The second correction pulse generation circuit generates a second correction pulse by detecting a phase difference between the second and third divided clock signals. The duty correction circuit checks whether the first and second correction pulses are generated at a preset logic level of the reference clock signal, and reflects the first or second correction pulses in a duty correction operation for the reference clock signal according to a result of the check.

Abstract: A semiconductor device comprises: a first or a second path configured to transmit a first signal which swings between a ground level and a first level, a third path configured to transmit a second signal which swings between the ground level and a second level lower than the first level, a transmitter configured to output received the first signal through the first or second path as the second signal to the third path, and initialize in response to an enable signal, and a receiver configured to output received the second signal through the third path as the first signal through the first or second path, determine level of the second signal through a reference level that is regulated according to a fed-back level of an output terminal thereof, and initialize in response to the enable signal.

Abstract: A data file reproducing method for a personal terminal which can include providing a data file by connecting a data supplying server to a communication network, selecting a data file, connecting the data supplying server to a personal terminal, transferring the selected data file to the personal terminal, and storing automatically the transferred data file in the personal terminal. A data reproducing apparatus for a personal terminal which can include a wireless transceiver that can transfer and receive data files to and from a mobile communication network, a storage device, a controller, a decoder and a reproducing unit.

Abstract: A data file reproducing method for a personal terminal which can include providing a data file by connecting a data supplying server to a communication network, selecting a data file, connecting the data supplying server to a personal terminal, transferring the selected data file to the personal terminal, and storing automatically the transferred data file in the personal terminal. A data reproducing apparatus for a personal terminal which can include a wireless transceiver that can transfer and receive data files to and from a mobile communication network, a storage device, a controller, a decoder and a reproducing unit.

Abstract: A multi-wefts inserting weaving machine, comprising a block arraying device comprising an upper plate and a lower plate which face each other and are movable upward and downward; and a plural number of unit blocks attached to the internal facing sides of the upper plate and the lower plate of the block arraying device through combining grooves, wherein the unit blocks include two grooves. Accordingly, a lattice woven structure can be easily woven from heavy-duty materials by the present multi-wefts inserting weaving machine.

Abstract: A data file reproducing method for a personal terminal which can include providing a data file by connecting a data supplying server to a communication network, selecting a data file, connecting the data supplying server to a personal terminal, transferring the selected data file to the personal terminal, and storing automatically the transferred data file in the personal terminal. A data reproducing apparatus for a personal terminal which can include a wireless transceiver that can transfer and receive data files to and from a mobile communication network, a storage device, a controller, a decoder and a reproducing unit.

Abstract: This invention discloses a method of manufacturing a semiconductor device, especially a method of forming field isolation, in which a portion of an active region around a field oxide film is highly-doped with the same type impurities as channel-stop impurity ions so that it changes a low-doped channel-stop region which results from a high temperature of field oxidation to a high-doped channel-stop region to prevent field inversion in device operation.