Patents by Inventor Chang Li

Chang Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12260130
    Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: March 25, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hang-Ting Lue, Tzu-Hsuan Hsu, Teng-Hao Yeh, Chih-Chang Hsieh, Chun-Hsiung Hung, Yung-Chun Li
  • Patent number: 12261125
    Abstract: A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer, wherein a first thickness of the conductive pillar is substantially equal to a sum of a second thickness of the second chip structure and a third thickness of the first conductive bump. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Heh-Chang Huang, Fu-Jen Li, Pei-Haw Tsao, Shyue-Ter Leu
  • Publication number: 20250092621
    Abstract: Disclosed are an easily maintainable assembly-type bridge expansion joint structure and a construction method thereof. The easily maintainable assembly-type bridge expansion joint structure, comprising: a to-be-connected bridge beam end, wherein a number of the to-be-connected bridge beam end is two, and a groove platform is provided on each of the two beam ends in an extending direction of a gap; a connecting box body, wherein a number of the connecting box body is two, each of the two connecting box bodies is fixedly arranged on the groove platform of the beam end, and a box chamber is provided on opposite side surfaces of the two connecting box bodies respectively, a plurality of box chambers are provided, which are open opposite each other, and the box chamber is provided in the extending direction of the gap; a side beam, wherein a number of the side beam is two.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 20, 2025
    Inventors: Duo LIU, Jiandong ZHANG, Xiaonan FENG, Runbo LIU, Chang YAN, Ming LI
  • Publication number: 20250096558
    Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first transistor and a clamping device. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first transistor is disposed on the second nitride semiconductor layer. The first transistor includes a first control electrode, a first current electrode and a second current electrode. The clamping device is disposed on the second nitride semiconductor layer and electrically coupled with the first transistor. The clamping device includes a second transistor and a third transistor electrically coupled with the second transistor. The clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 20, 2025
    Applicant: INNOSCIENCE (SUZHOU) SEMICONDUCTOR CO., LTD.
    Inventors: Chang CHEN, Xiaoming LIU, Xinyu LI
  • Publication number: 20250098506
    Abstract: A display apparatus, including: a display panel; a supporting layer, provided on a backlight side of the display panel; a circuit board, provided on a side of the supporting layer away from the display panel; and a shielding layer, overlaid on a side of the circuit board away from the display panel and including a first insulation layer and a conductive layer. The conductive layer includes a shielding portion and a leading-out portion; the first insulation layer exposes at least partial region of the leading-out portion; an orthographic projection of the shielding portion on the display panel is located within an orthographic projection of the circuit board on the display panel; an orthographic projection of the leading-out portion on the display panel is located outside the orthographic projection of the circuit board on the display panel; the leading-out portion is electrically connected to the supporting layer.
    Type: Application
    Filed: July 4, 2022
    Publication date: March 20, 2025
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Chang LIU, Jiaxiang WANG, Xinqi LIN, Jie YANG, Yaqi LI, Binfeng FENG, Yanli WANG
  • Patent number: 12256391
    Abstract: A terminal device obtains first configuration information, where the first configuration information includes indication information of a UL MAC CE. Then, the terminal device preferentially sends a UL MAC PDU or an SL MAC PDU based on the indication information, where the UL MAC PDU can be used to transmit the UL MAC CE.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: March 18, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiangyu Li, Xiao Xiao, Chang Yu, Jun Wang, Wenjie Peng, Mingzeng Dai, Dongdong Wei
  • Patent number: 12256202
    Abstract: The invention discloses a stereo enhancement system and a stereo enhancement method. The stereo enhancement system includes a beamforming unit and a signal processing unit. The beamforming unit is used for receiving a plurality of input sound signals and generating a plurality of beamforming sound signals corresponding to a plurality of direction intervals respectively. The signal processing unit is coupled to the beamforming unit and used for receiving the plurality of beamforming sound signals corresponding to the plurality of direction intervals respectively and generating a first synthesized output sound signal and a second synthesized sound signal accordingly.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: March 18, 2025
    Assignee: INTELLIGO TECHNOLOGY INC.
    Inventors: Chia-Ping Chen, Chih-Sheng Chen, Hua-Jun Hong, Chien-Hua Hsu, Jen-Feng Li, Wei-An Chang, Tsung-Liang Chen
  • Publication number: 20250083204
    Abstract: Embodiments of the present disclosure disclose a Cupriavidus metallidurans CML2, wherein the Cupriavidus metallidurans CML2 is deposited in the China Center for Type Culture Collection with a depository number CCTCC NO: M20231365, and a 16s rDNA of the Cupriavidus metallidurans CML2 has a nucleotide sequence of SEQ ID No. 1.
    Type: Application
    Filed: February 27, 2024
    Publication date: March 13, 2025
    Applicant: HUBEI UNIVERSITY
    Inventors: Xuejing YU, Yong YANG, Yuan ZHANG, Xianhua ZHANG, Yadong LI, Shan WU, Linjie LI, Chang GAO, Yue LU, Tong WU
  • Publication number: 20250089295
    Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Yan-Ting Lin, Yen-Ru Lee, Chien-Chang Su, Chih-Yun Chin, Chien-Wei Lee, Pang-Yen Tsai, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20250081822
    Abstract: Provided is a display panel, including a driver backplane, a light-emitting functional layer, and a light-extraction layer. The light-emitting functional layer and the light-extraction layer are successively stacked on a bearing surface of the driver backplane. The light-emitting functional layer includes a plurality of light-emitting units arranged in arrays. The light-extraction layer includes a first sub-layer and a second sub-layer, which are successively stacked on the light-emitting functional layer. A refractive index of the first sub-layer is less than a refractive index of the second sub-layer. A plurality of grooves are defined in the first sub-layer, and each of the plurality of grooves is opposite to one of the plurality of light-emitting units. A portion of the second sub-layer is within the plurality of grooves. A boundary length of the groove is greater than a boundary length of a light-emitting region of the corresponding one of the light-emitting units.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 6, 2025
    Inventors: Ping WEN, Chang LUO, Yi ZHANG, Zeyu LI, Conglei ZHANG, Bo SHI
  • Patent number: 12242389
    Abstract: An application-level memory control group of a first application may be created when the first application is opened. An anonymous page of the first application is added to a least recently used linked list of the application-level memory control group, and a file page of the first application is added to a global least recently used linked list. An application-level memory control group is created in a dimension of an application, and an anonymous page of the application is managed in a refined manner. In addition, a file page of the application-level memory control group may be managed based on a global least recently used linked list.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: March 4, 2025
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventors: Wei Han, Chang Xie, Qinxu Pan, Jian Chen, Qiang Gao, Song Liu, Jinxuan Fang, Yuanfeng Hu, Xiangbing Tang, Weilai Zhou, Cai Sun, Zuoyu Wu, Qing Xia, Wei Du, Biao He, Fa Wang, Chengke Wang, Ziyue Luo, Zongfeng Li, Xu Wang, Xiyu Zhou, Yu Liu, Tao Li, Long Jin, Di Fang
  • Patent number: 12242781
    Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.
    Type: Grant
    Filed: November 13, 2023
    Date of Patent: March 4, 2025
    Assignee: ANSYS, INC.
    Inventors: Norman Chang, Hsiming Pan, Jimin Wen, Deqi Zhu, Wenbo Xia, Akhilesh Kumar, Wen-Tze Chuang, En-Cih Yang, Karthik Srinivasan, Ying-Shiun Li
  • Patent number: 12244758
    Abstract: Methods and systems are described for authenticating calls. An example method may comprise receiving a message indicative of a call request. Header data associated with the message may be analyzed to determine an attestation value. A signature may be generated based on the attestation value. A signed message comprising the signature and at least a portion of the message may be sent.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: March 4, 2025
    Assignee: Comcast Cable Communications, LLC
    Inventor: Chia-Chang Li
  • Publication number: 20250071371
    Abstract: The disclosure relates to the technical field of computer processing, and discloses a method, an apparatus, a device and a storage medium for processing playing loudness of media data. The method according to the disclosure comprises obtaining media data to be played and an audio feature of the media data to be played; obtaining loudness requirement information, wherein the loudness requirement information comprises a current playing environment and/or an attribute of a playing device; determining loudness processing information for the media data to be played based on the audio feature and the loudness requirement information; and processing the media data to be played based on the loudness processing information to obtain target media data for playing.
    Type: Application
    Filed: August 20, 2024
    Publication date: February 27, 2025
    Inventors: Ye MA, Chang Xiao, Shilei Liu, Tong Wu, Zhiguang Zhang, Xin Zhang, Jing Li, Shichao Ge, Hao Huang
  • Publication number: 20250064345
    Abstract: A gait evaluating system including a processor is provided. The processor identifies whether a gait type of the user belongs to a normal gait, a non-neuropathic gait or a neuropathic gait based on step feature values of a user and walking limb feature values of the user. In response to that the gait type of the user belongs to the non-neuropathic gait, the processor controls the display panel to display a first auxiliary information, a second auxiliary information, and a third auxiliary information. The first auxiliary information indicates a potential sarcopenia of the user. The second auxiliary information indicates a dietary guideline for muscle building and muscle strengthening. The third auxiliary information shows a motion instruction video for regaining or maintaining muscle strength of the user.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 27, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Je-Ping Hu, Keng-Hsun Lin, Shih-Fang Yang Mao, Pin-Chou Li, Jian-Hong Wu, Szu-Ju Li, Hui-Yu Cho, Yu-Chang Chen, Yen-Nien Lu, Jyun-Siang Hsu, Nien-Ya Lee, Kuan-Ting Ho, Ming-Chieh Tsai, Ching-Yu Huang
  • Publication number: 20250072007
    Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Cheng-Tung Huang, Jen-Yu Wang, Yung-Ching Hsieh, Po-Chun Yang, Jian-Jhong Chen, Bo-Chang Li
  • Publication number: 20250067667
    Abstract: There is provided an optical machine of a smoke detector including a substrate, a light source, a light sensor and a light blocking member. The light source and the light sensor are arranged on the substrate in a first direction. The light blocking member is arranged upon the light source and blocks a part of an emission angle of the light source in the first direction far away from the light sensor.
    Type: Application
    Filed: November 15, 2024
    Publication date: February 27, 2025
    Inventors: CHENG-NAN TSAI, Yen-Chang Chu, Chih-Ming Sun, Chi-Chih Shen, Kuo-Hsiung Li
  • Patent number: 12233099
    Abstract: The present invention relates to a composition for promoting myogenesis, containing, as an active ingredient, a processed ginseng extract in which a trace amount of a ginsenoside ingredient is increased. It has been ascertained that the processed ginseng extract promotes the differentiation of myoblasts into muscle and inhibits muscle atrophy caused by myostatin, which is a myogenesis inhibitory factor, and thus it is expected that a composition for preventing or treating muscle disorder-related diseases, having excellent effects, can be developed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 25, 2025
    Assignee: GREEN CROSS WELLBEING CORPORATION
    Inventors: Sun Kyu Park, Jeom Yong Kim, Young Hyo Yoo, Min Jung Jang, Chang Taek Oh, Min Ju Lim, Gwan Su Yi, Yi Li, Yoon Hyeok Lee, Jae Cheal Yoo
  • Patent number: 12236899
    Abstract: The present disclosure provides a display panel, a method for preparing the same, and a display device. The display panel includes pixel units distributed in an array in a display area, where the pixel units include sub-pixels, at least one of which has a maximum grayscale value voltage different from a maximum grayscale value voltage of the other sub-pixel; and a switching circuit including switching units on a side of the display area, where one end of the switching unit is connected to a data line. In two adjacent columns of pixel units, two sub-pixels having the same maximum grayscale value voltage are connected to two adjacent switching units through data lines, respectively.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: February 25, 2025
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zheng Bao, Mingqiang Wang, Ziqian Li, Yi Zhang, Xiangdong Wei, Gong Chen, Haotian Yang, Chang Wang, Jiaxiang Zhang, Bin Zhang
  • Patent number: D1065187
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: March 4, 2025
    Assignee: Siemens Aktiengesellschaft
    Inventors: Yong Jie Sun, Hai Jun Pang, Chang Sen Chen, Ting Li Lan, Zhan Bo Ren