Abstract: Provided herein is technology relating to automated driving and particularly, but not exclusively, to an intelligent information conversion system and related methods for providing collaborative automatic driving to intelligent transportation systems, vehicle networking systems, collaborative management control systems, vehicle-road collaborative systems, automated driving systems, and the like.

Abstract: An approach for optimizing statistical query performance. The approach receives a structured query language set. The approach identifies a first set of parameters associated with the statements of the SQL set. The approach creates a merged SQL statement based on one or more matching parameters of SQL statements in the SQL set. The approach binds a second set of parameters associated with the merged SQL statement to the merged SQL statement. The approach generates a SQL statement based on the merged SQL statement. The approach generates a remote SQL statement based on the SQL statement. The approach executes a commit statement on the remote SQL statement.

Abstract: There is provided a physiological detection device including a light source, a light detector, a processing unit and a display device. The light source emits light to illuminate a skin surface. The light detector receives the light from the skin surface to output detected signals. The processing unit confirms an attached state according to the detected signals and controls the display device to show an indication signal or a warning message when the attached state is confirmed not good.

Abstract: There is provided an optical machine of a smoke detector including a substrate, a light source, a light sensor and a light blocking member. The light source and the light sensor are arranged on the substrate in a first direction. The light blocking member is arranged upon the light source and blocks a part of an emission angle of the light source in the first direction far away from the light sensor.

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

Abstract: The disclosure provides binding proteins that bind PD-L1 and CD137 (PD-L1/CD137 bispecific), binding proteins that bind PD-L1 and TGF? (PD-L1/TGF? bispecific), binding proteins that bind PD-L1, TGF?, and CD137 (PD-L1/TGF?/CD137 trispecific), and binding proteins that bind CD137, TGF?, and PD-L1 (CD137/TGF?/PD-L1 trispecific). The disclosure also provides pharmaceutical compositions comprising these binding proteins, and methods of their use to treat and/or prevent cancer.

Abstract: The present application relates to a nano-liter photoionization mass spectrometry ion source device and an operation method thereof. The nano-liter photoionization mass spectrometry ion source device includes a nano-tip, configured to load a sample solution, thus achieving a nano-electrospray process; a metal electrode, inserted into the nano-tip to contact with the sample solution directly, thus providing a high-voltage electric field for the nano-electrospray; and a UV lamp, configured to emit a high-energy ultraviolet photon to be combined with a gaseous molecule obtained by vaporizing the sample solution, thus achieving a photoionization process. Directed to the problems such as low ionization efficiency, poor sensitivity and more impurity interference existing in the unicellular mass spectrometry process of trace low-polar compounds in small-volume samples, a nano-liter photoionization mass spectrometry ion source device suitable for the analysis on low-polar compounds in small volume, e.g.

Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.

Abstract: A compound of Formula (0): where Ar is one or more substituted or unsubstituted aromatic units, R is independently H, F, CN, a C1-C20 linear or branched aliphatic group or a C1-C20 linear or branched aliphatic acyl group, and n is an integer 3 or greater, is useful for sorting and dispersing carbon nanotubes (CNTs) and for producing printed electronic devices (e.g. CO2 sensors, TFTs) in which the CNTs are functionalized with the compound.

Abstract: A structure for holding a battery on an automated guided vehicle (AGV) so as to allow easy and convenient battery replacement includes two fixed supports and a bracket. The bracket is connected between the two supports and each support defines a vertical groove and two horizontal grooves. Two sliders at the ends of the bracket are insertable into either horizontal groove. The two sliders can move down along the vertical groove together until the bracket makes contact with the battery and holds it in place. The two sliders can move up along the vertical groove and sideways into the horizontal grooves, thereby unlatching and releasing the battery for rapid replacement. An AGV using the structure is also disclosed.

Abstract: Disclosed is a boronic acid derivative. Provided are a compound of formula (I) or a pharmaceutically acceptable salt, solvate, polymorph or isomer thereof, a pharmaceutical composition containing the same, and the use thereof in the treatment of lmp7-related diseases.

Abstract: A power module structure is provided. The power module structure includes a substrate, a chip, a first metal structure, a second metal structure and a packaging material. The chip, the first metal structure and the second metal structure are disposed on the substrate. From a cross-sectional view, the width of the first metal structure is greater than the width of the second metal structure. The packaging material covers the substrate and the chip, and the portions of the first metal structure and the second metal structure are exposed from the upper surface of the packaging material.

Abstract: Methods of forming and a semiconductor devices where the channel region includes a germanium-comprising layer; and a crystalline silicon layer on the germanium-comprising layer. A gate structure over a first surface and a second surface, the second surface opposing the first surface. In some implementations, the crystalline silicon layer can mitigate damage during processing.

Abstract: A circuit includes a first Dual Interlocked Storage Cell (DICE) component, a second DICE component, a third DICE component, and a fourth DICE component operatively coupled to one another as a loop. The first and second DICE components form a first sub-latch configured to receive an input signal, the third and fourth DICE components form a second sub-latch configured to receive the same input signal, the first sub-latch is configured to provide, at a first node, an intermediate signal based on the input signal, and the second sub-latch is configured to provide, at a second node, the same intermediate signal based on the input signal. The circuit includes a first inverter configured to logically invert the intermediate signal and provide, at a third node, an output signal. The circuit includes a second inverter configured to logically invert the intermediate signal and provide, at the third node, the output signal.

Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

Abstract: Disclosed is a method for convolution calculation in a neural network, comprising: reading an input feature map, depthwise convolution kernels and pointwise convolution kernels from a dynamic random access memory (DRAM); performing depthwise convolution calculations and pointwise convolution calculations by depthwise convolution calculation units and pointwise convolution calculation units, according to the input feature map, the depthwise convolution kernels and the pointwise convolution kernels to obtain output feature values of a first predetermined number p of points on all pointwise convolution output channels; storing the output feature values of a first predetermined number p of points on all pointwise convolution output channels into an on-chip memory; and repeating above operation to obtain output feature values of all points on all point wise convolution output channels. Therefore, the storage space for storing intermediate results may be reduced.

Abstract: The present application relates to a light emitting device, manufacturing method thereof, and a display device provided therewith. The light emitting device may include: a substrate; a first electrode provided on the substrate, and a second electrode disposed on a plane identical with a plane of the first electrode at a position spaced apart from the first electrode; at least one light emitting element provided on the substrate, and including a first end and a second end with respect to a longitudinal direction; a bridge pattern provided on the light emitting element, and coupled to the second end of the light emitting element; a first contact electrode provided on the substrate, and coupling the first electrode with the first end of the light emitting element; and a second contact electrode provided on the substrate, and coupling the bridge pattern with the second electrode.

Abstract: A layout structure of a memory cell array for a non-volatile memory is provided. The memory cell array includes plural memory cells. Each memory cell includes a capacitor, an erase gate element, a select transistor, a floating gate transistor and a switch transistor. Moreover, plural wells are formed in a semiconductor substrate, and a floating gate is formed over the semiconductor substrate. The locations of the well regions and the shape of the floating gate are specially designed. Moreover, the plural memory cells with at least two shapes are constructed on the semiconductor substrate. Consequently, the layout area of the layout structure of the memory cell array can be effectively reduced.