Patents by Inventor Chang Lin

Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12040300
    Abstract: A semiconductor package includes a first die, a second die, and a hybrid-type adhesive. The second die is stacked on the first die through the hybrid-type adhesive. The hybrid-type adhesive includes a conductive adhesive and a non-conductive adhesive. The conductive adhesive is disposed between the non-conductive adhesive and the first die. The non-conductive adhesive is disposed between the conductive adhesive and the second die.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: July 16, 2024
    Assignee: Airoha Technology Corp.
    Inventors: Ying-Chih Chen, Min-Yu Lin, Kuo-Chang Chang, Jen-Chan Huang
  • Patent number: 12039122
    Abstract: A touch apparatus includes a touch screen and a touch controller. The touch controller is configured to process touch sensing signals received from the touch screen to generate a touch coordinate with respect to a touch event occurring on the touch screen. The touch screen includes a plurality of first touch sensing electrodes and a plurality of second touch sensing electrodes. The first touch sensing electrodes are disposed in a center area of the touch screen, wherein at least one part of the first touch sensing electrodes are rectangular. The second touch sensing electrodes are disposed in an edge area of the touch screen surrounding the center area, wherein each of the second touch sensing electrodes is corresponding to a central angle and a plurality of central angles corresponding to the plurality of second touch sensing electrodes substantially equal.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: July 16, 2024
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yi-Ying Lin, Chih-Chang Lai
  • Patent number: 12039242
    Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Pochun Wang, Jerry Chang Jui Kao, Jung-Chan Yang, Hui-Zhong Zhuang, Tzu-Ying Lin, Chung-Hsing Wang
  • Patent number: 12040382
    Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 12040800
    Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien
  • Publication number: 20240233590
    Abstract: An electronic device and a manufacturing method thereof are provided. The manufacturing method of the electronic device includes the following. A substrate is provided. A plurality of electronic units are transferred to the substrate. The electronic units are inspected to obtain M first defect maps. The M first defect maps are integrated into N second defect maps, where N<M. M repairing groups are provided according to the N second defect maps. Each of the repairing groups includes at least one repairing electronic unit. The M repairing groups are transferred to the substrate. At least two of the repairing groups have the same location distribution of repairing electronic units, and the location distribution is consistent with a defect distribution of one of the second defect maps.
    Type: Application
    Filed: September 18, 2023
    Publication date: July 11, 2024
    Applicant: Innolux Corporation
    Inventors: Kai Cheng, Fang-Ying Lin, Ming-Chang Lin, Tsau-Hua Hsieh
  • Publication number: 20240236572
    Abstract: An audio latency calibration method is disclosed. A master speaker and a slave speaker are located at a separation distance from each other, and a paring process is performed. As the paring process is completed, multiple latency time period parameters are obtained relating to the master and slave speakers. The latency time period parameters comprise: T1+T2 representing the time that the master speaker sends an audio signal to the slave speaker, T3+T4 representing the time that the audio signal is transmitted from the slave speaker to a microphone of the master speaker, T5 representing the time that a trumpet of the master speaker plays the audio signal and T3? representing the time that a microphone of the master speaker receives the audio signal. Thus, the way to synchronously play audio signals can be achieved.
    Type: Application
    Filed: January 5, 2023
    Publication date: July 11, 2024
    Inventor: PO-CHANG LIN
  • Publication number: 20240234419
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 11, 2024
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Lo Heng CHANG, CHIH-HAO WANG, Chien Ning YAO, Kuo-Cheng CHIANG
  • Patent number: 12034004
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: July 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhi-Chang Lin, Huan-Chieh Su, Kuo-Cheng Chiang
  • Patent number: 12034062
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.
    Type: Grant
    Filed: November 4, 2022
    Date of Patent: July 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Patent number: 12033331
    Abstract: A method for detecting motion information includes the following steps. First, a pixel array is provided for detecting an image of a measured object located in a first distance range or in a second distance range, and the pixel array includes a plurality of invisible image sensing pixels and a plurality of visible image sensing pixels. Then, image detection is conducted within the first distance range by using the invisible image sensing pixels to output a plurality of invisible images. Next, the image detection is conducted within the second distance range by using the visible image sensing pixels to output a plurality of visible images. Then, the plurality of invisible images and the plurality of visible images are analyzed by using a processing unit, so as to obtain motion information of the measured object. A pixel array for detecting motion information and an image sensor are also provided.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: July 9, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Han-Chang Lin, Shu-Sian Yang, Shih-Feng Chen
  • Patent number: 12032224
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: July 9, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Sin-Hong Lin, Yung-Ping Yang, Wen-Yen Huang, Yu-Cheng Lin, Kun-Shih Lin, Chao-Chang Hu, Yung-Hsien Yeh, Mao-Kuo Hsu, Chih-Wei Weng, Ching-Chieh Huang, Chih-Shiang Wu, Chun-Chia Liao, Chia-Yu Chang, Hung-Ping Chen, Wei-Zhong Luo, Wen-Chang Lin, Shou-Jen Liu, Shao-Chung Chang, Chen-Hsin Huang, Meng-Ting Lin, Yen-Cheng Chen, I-Mei Huang, Yun-Fei Wang, Wei-Jhe Shen
  • Publication number: 20240223058
    Abstract: An industrial heavy load electric linear actuator includes a gearbox, an electric motor, a lead screw, an extension pipe and a load baring structure. The electric motor is connected to the gearbox. A portion of the lead screw is received inside the gearbox and driven by the electric motor, and another portion of the lead screw is extended out of the gearbox. The extension pipe is movably fastened to the lead screw. The load bearing structure includes a sleeve, a bearing, a fastening element, a fixation seat, and a rear supporting seat. The sleeve is mounted to the lead screw and holds the bearing jointly with the fastening element. The fixation seat and the rear supporting seat hold the bearing at outer perimeters of the sleeve and the fastening element.
    Type: Application
    Filed: March 19, 2024
    Publication date: July 4, 2024
    Inventor: Yu-Chang LIN
  • Publication number: 20240219332
    Abstract: An electrical impedance imaging sensing system includes a signal processing device, a sensing element and a processor. The signal processing device is electrically coupled to the sensing element and configured for outputting an emission signal. Each of N electrodes of the sensing element is configured to receive a received signal after the emission signal passes through a to-be tested object. The processor is configured to determine whether one of the N electrodes fails according to a plurality of the received signal; in response to the failure of the electrode, compensate the received signal of the failed electrode; and generate an electrical impedance image pre-processing data according to the received signal.
    Type: Application
    Filed: December 12, 2023
    Publication date: July 4, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Lin HU, Zong-Yan LIN, I-Cheng CHENG, Chien-Ju LI, Chii-Wann LIN
  • Patent number: 12025171
    Abstract: A tamper-proof screw includes a main body, a pin body, a ball, and at least one abutting member. A through hole is provided in the main body. The pin body is movably disposed in the through hole. The ball is located in the through hole. The abutting member is located in the through hole and has a connecting end and a free end opposite to each other. The connecting end is disposed on an inner wall of the main body and located between the ball and the free end. The ball is located between the pin body and the abutting member. When the pin body moves in the through hole to push the ball to press against the connecting end of the abutting member, the abutting member pivots around the connecting end to allow the free end to extend outwards from the main body.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: July 2, 2024
    Assignees: MAINTEK COMPUTER (SUZHOU) CO., LTD, PEGATRON CORPORATION
    Inventor: Chang-Lin Zhang
  • Patent number: 12021082
    Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Hou-Yu Chen, Yong-Yan Lu
  • Patent number: 12014992
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Chien-Chang Lin
  • Publication number: 20240194758
    Abstract: A method for forming a gate all around transistor includes forming a plurality of semiconductor nanosheets. The method includes forming a cladding inner spacer between a source region of the transistor and a gate region of the transistor. The method includes forming sheet inner spacers between the semiconductor nanosheets in a separate deposition process from the cladding inner spacer.
    Type: Application
    Filed: February 22, 2024
    Publication date: June 13, 2024
    Inventors: Zhi-Chang LIN, Kuan-Ting PAN, Shih-Cheng CHEN, Jung-Hung CHANG, Lo-Heng CHANG, Chien-Ning YAO, Kuo-Cheng CHIANG
  • Patent number: 12009410
    Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu
  • Patent number: 12009912
    Abstract: An optical device includes a first waveguide, ring-shaped waveguides adjacent to the first waveguide, and heaters coupled to the ring-shaped waveguides in one-to-one correspondence. A method includes coupling a first light source with a first wavelength to the first waveguide, increasing electric current through the heaters until a first one of the ring-shaped waveguides resonates, assigning the first one of the ring-shaped waveguides to the first wavelength, resetting the electric current through the heaters to the initial electric current, coupling a second light source with a second wavelength to the first waveguide wherein the second wavelength is different from the first wavelength, increasing the electric current through the heaters until a second one of the ring-shaped waveguides resonates wherein the second one of the ring-shaped waveguides is different from the first one of the ring-shaped waveguides, and assigning the second one of the ring-shaped waveguides to the second wavelength.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Stefan Rusu, Weiwei Song, Lan-Chou Cho