Abstract: A smart ring with a physiological feature detecting method is applied to a target object. The smart ring includes a pressure sensor and an operation processor. The pressure sensor is adapted to detect a pressure value of the target object applied for the smart ring. The operation processor is electrically connected with the pressure sensor, and adapted to compare the pressure value with a preset condition and determine a behavior of the target object according to a comparison result of the pressure value and the preset condition for generating a related operation command.

Abstract: A an electric deck frame structure (1, 1A) includes: corner lifting vertical posts (10), each having a carrying seat (11) and a retractable rod (12), the carrying seat includes a first connection part (111) having a first electric connection assembly (1133) and a second connection part (116) having a second electric connection assembly (1183); connection pipes (20), connected to the corner lifting vertical posts (10) and having a first opening (21) and a second opening (22); a transformer (30) having an electricity input port (31) arranged corresponding to the first opening (21) and an electricity output port (32) arranged corresponding to the second opening (22), the transformer is hidden in the connection pipe, and a power and signal main cable (40), connected to the electricity output port (32), the first electric connection assembly (1133) and the second electric connection assembly (1183).

Abstract: A wearable device is provided. The wearable device includes an electronic component and an encapsulant. The encapsulant includes a low-penetrability region encapsulating the electronic component and a high-penetrability region physically separated from the electronic component.

Abstract: A probe head includes an upper pin holder and a lower pin holder coupled to the upper pin holder. A pin arrangement space is defined between the upper pin holder and the lower pin holder. A conductive film is disposed between the upper pin holder and the lower pin holder. A plurality of probe pins penetrates through the upper pin holder, the conductor film and the lower pin holder, and extends outwardly from a bottom surface of the lower pin holder.

Abstract: An audio latency calibration method is disclosed. A master speaker and a slave speaker are located at a separation distance from each other, and a paring process is performed. As the paring process is completed, multiple latency time period parameters are obtained relating to the master and slave speakers. The latency time period parameters comprise: T1+T2 representing the time that the master speaker sends an audio signal to the slave speaker, T3+T4 representing the time that the audio signal is transmitted from the slave speaker to a microphone of the master speaker, T5 representing the time that a trumpet of the master speaker plays the audio signal and T3? representing the time that a microphone of the master speaker receives the audio signal. Thus, the way to synchronously play audio signals can be achieved.

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other; forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species; implanting fluorine ions into the source/drain epitaxial structure; after implanting fluorine ions into the source/drain epitaxial structure, performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and forming a source/drain contact over the source/drain epitaxial structure.

Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.

Abstract: A cover structure of a control box is disclosed. The control box includes a base with a limiting part, the cover structure includes a cover body, a knob and a torsion spring, the cover body is connected to the base, the knob is rotatably connected to the cover body and has a stop arm stopped at the limiting part, two ends of the torsion spring are fixed to the cover body and the knob respectively to generate a pre-torque. When the knob is rotated by an external force, the stop arm is released from the limiting part to unlock the cover structure from the base, and when the external force is removed, the knob restores to original position by the pre-torque. Therefore, the cover structure may be removed from the base quickly to facilitate an operator's use and maintenance.

Abstract: Methods are proposed to define UE behavior for performing synchronization signal block (SSB) based radio link monitoring (RLM) and channel state information reference signal (CSI-RS) based RLM. In a first novel aspect, if CSI-RS based RLM-RS is not QCLed to any CORESET, then UE determines that CSI-RS RLM configuration is error and does not perform RLM accordingly. In a second novel aspect, SSB for RLM and RLM CSI-RS resources are configured with different numerologies. UE perform SSB based RLM and CSI-RS based RLM based on whether the SSB and CSI-RS resources are TDMed configured by the network. In a third novel aspect, when multiple SMTC configurations are configured to UE, UE determines an SMTC period and whether SMTC and RLM-RS are overlapped for the purpose of RLM evaluation period determination.

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

Abstract: The present disclosure provides a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. The present disclosure also includes forming a trench between neighboring source/drain features to remove bridging between the neighboring source/drain features. In some embodiments, the trenches between the source/drain features are formed by etching from the backside of the substrate.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

Abstract: An electronic system including an image sensor, a face detection engine, an eye detection engine and an eye protection engine is provided. The image sensor captures an image. The face detection engine recognizes a user face in the image. The eye detection engine recognizes user eyes in the image. The eye protection engine turns off a display device when the user eyes are recognized in the image but the user face is not recognized in the image.

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

Abstract: Provided is a circuit board structure including a substrate, a loop-wrapping ground layer, an insulating structure, a first build-up layer, a top wiring layer, a bottom wiring layer, a first conductive via, and a plurality of second conductive vias. The aforementioned structure defines a signal transmitting structure. An equivalent circuit of the signal transmitting structure at least includes a first equivalent circuit, a second equivalent circuit, a third equivalent circuit and a fourth equivalent circuit, which correspond to different uniform transmitting sections respectively. The first equivalent circuit, the second equivalent circuit, the third equivalent circuit and the fourth equivalent circuit are connected in series with each other according to an ABCD transmission matrix series connection principle.

Abstract: A nanoFET transistor includes doped channel junctions at either end of a channel region for one or more nanosheets of the nanoFET transistor. The channel junctions are formed by a iterative recessing and implanting process which is performed as recesses are made for the source/drain regions. The implanted doped channel junctions can be controlled to achieve a desired lateral straggling of the doped channel junctions.

Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.