Abstract: A light source assembly includes a first annular reflector, a second annular reflector and a plurality of first light source modules. The first annular reflector has a first reflective surface. The second annular reflector is coaxial with the first annular reflector. A radius of the first annular reflector is greater than that of the second annular reflector. The second annular reflector has a second reflective surface facing the first reflective surface. The first light source modules take a central axis of the first annular reflector as a center and annularly arranged around the center. The first light source modules provide first beams to the first reflective surface, which reflects the first beams to the second reflective surface. The second reflective surface reflects the first beams and makes the first beams emit along a direction parallel to a central axis of the second annular reflector. A projection device is also provided.

Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.

Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.

Abstract: A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuations in the input and output clock rates, and allows adjustment of the ratio of the input and output the number of lines per frame or number of pixels per line so that output device specifications are not exceeded. A single integrated circuit may provided which is adapted to perform a plurality of techniques, and includes resources by which the user is able to enable and disable such techniques as needed for the particular bridging operation being executed.

Abstract: An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself, as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed.

Abstract: A video format bridge employs a plurality of techniques to insure that the line buffer does not suffer underflow or overflow conditions, and that the output frame rate matches the input frame rate. The bridge handles the problem of residue lines, addresses fluctuations in the input and output clock rates, and allows adjustment of the ratio of the input and output the number of lines per frame or number of pixels per line so that output device specifications are not exceeded. A single integrated circuit may provided which is adapted to perform a plurality of techniques, and includes resources by which the user is able to enable and disable such techniques as needed for the particular bridging operation being executed.

Abstract: An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself, as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed.

Abstract: An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself; as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed.

Abstract: A system and process for logic extraction from the layout of logic blocks is described. Logic design information is extracted from a transistor level net list which is stored in a memory. The transistor level net list in turn is generated from a layout polygon database using techniques in the art. The process comprises processing the transistor level net list in the memory to define groups of transistors according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage and the transistor type. The groups of transistors are analyzed according to their interconnections, and their membership in groups. Finally, logic units are identified in response to the step of analyzing the groups of transistors.

Abstract: An architecture for an integrated circuit with in-circuit programming, allows for dynamically altering the in-circuit programming instruction set itself, as well as other software stored on the chip. The architecture is based on a microcontroller on an integrated circuit having two or more banks of embedded non-volatile memory arrays which store instructions, including an in-circuit programming instruction set. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a remote partner, and updates data and software, including the in-circuit programming instruction set, when needed.

Abstract: An architecture for an integrated circuit with in-circuit programming includes a microcontroller on an integrated circuit and one or more banks of non-volatile memory which store instructions, including an in-circuit programming (ICP) set of instructions. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a device external to the integrated circuit and uses data obtained in the exchange to update software for the microcontroller. Portions of the ICP code which are likely to change between different application environments are stored in reprogrammable flash memory cells. Other portions of the ICP code, which are not likely to change between different application environments, are stored in space-efficient mask ROM memory cells. In this way, the ICP system can be flexibly adapted to different application environments, while conserving on silicon area occupied the ICP system.

Abstract: A method and system is disclosed for efficiently transferring a sequence of data words from an I/O device to sequential addresses in a main memory via an I/O bridge. The sequence of data words to be transferred includes one or more subsequences of data words. Each subsequence of data words include only data words destined to addresses of the main memory in which data words of only one data line are stored. The I/O bridge has control logic for receiving a first subsequence of data words corresponding to a currently owned data line and for claiming ownership in one or more of the very next data lines corresponding to the next subsequences of data words to be transferred from the I/O device. The I/O bridge also has a buffer memory for storing a subsequence of the sequence of data words received from the I/O device.

Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.