Abstract: An LCoS display pixel structure is disclosed. According to at least one embodiment, the present disclosure provides an LCoS display pixel structure which implements a pattern or geometry having an analog pixel structure in a display having micro-display LCoS structures.

Abstract: A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.

Abstract: A semiconductor integrated circuit includes at least one pad coupled to a bus line, a transmitter for transmitting a signal from an internal circuit to the outside through the pad, and a termination circuit for terminating the bus line. The transmitter and the termination circuit are disposed to surround the pad, reducing a size of the semiconductor integrated circuit.

Abstract: A data output circuit includes a plurality of registers and a plurality of register output selection switches that are respectively connected to the plurality of registers. Pairs of the plurality of register output selection switches are connected by respective common active regions. A first data group selection switch is connected to the common active regions of a first set of the plurality of register output selection switches. A second data group selection switch is connected to the common active regions of a second subset of the plurality of register output selection switches. An output driver is connected to the first and second data group selection switches.

Abstract: An integrated circuit device includes first and second complementary data line pairs, e.g., global or local I/O data line pairs, disposed on a substrate and extending along a first direction, the first and second complementary data line pairs arranged such that first and second data lines of the first complementary data line pair have a first data line of the second complementary data line pair disposed therebetween. An equalization transistor includes respective first and second source/drain regions in the substrate that are coupled to respective ones of the first and second data lines of the first complementary data line pair and an equalization transistor gate electrode disposed on the substrate between the first and second data lines of the first complementary data line pair.

Abstract: An integrated circuit device includes first and second complementary data line pairs, e.g., global or local I/O data line pairs, disposed on a substrate and extending along a first direction, the first and second complementary data line pairs arranged such that first and second data lines of the first complementary data line pair have a first data line of the second complementary data line pair disposed therebetween. An equalization transistor includes respective first and second source/drain regions in the substrate that are coupled to respective ones of the first and second data lines of the first complementary data line pair and an equalization transistor gate electrode disposed on the substrate between the first and second data lines of the first complementary data line pair.

Abstract: A semiconductor integrated circuit includes at least one pad coupled to a bus line, a transmitter for transmitting a signal from an internal circuit to the outside through the pad, and a termination circuit for terminating the bus line. The transmitter and the termination circuit are disposed to surround the pad, reducing a size of the semiconductor integrated circuit.

Abstract: An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

Abstract: An integrated circuit comprises a substrate having circuitry integrated with the substrate. Switching circuitry is selectably operable to configure signal paths to alternative mirrored pads over the substrate. At least one of the first and second signal paths may comprise a buffer in series between the switching circuit and its respective pad.

Abstract: Disclose is a semiconductor memory device including a plurality of memory cell arrays, row and column decoders for selecting/driving each memory cell, and a plurality of bit line sensing amplifier arrays for sensing data of each memory cell, the semiconductor memory device comprising: a plurality of sub word line driver sections for driving each memory cell with a sub word line enable selection signal (SWLE) decoded by LSB address and with a global word line signal (GWLb) decoded by MSB address in the row decoder; a row decoding precharge signal generating section (RDPRi/VBFi) for applying a precharge signal to the row decoder and a voltage Vbb to the GWLb signal by means of the MSB address PXb; a level shifting section for shifting and transmitting an output signal from the column decoder to column selection lines which connects the column decoder with the bit line sensing amplifier array in series; and a data input/output controlling section for selectively applying an active signal to the bit line sensing

Abstract: The semiconductor memory according to the present invention employs a plurality of sense amplifier drivers which individually control the sense amplifiers, or control groups of sense amplifiers, in the semiconductor memory. More specifically, the sense amplifier drivers control whether associated sense amplifiers are connected to sense amplifier array input/output lines. In this manner fewer sense amplifiers are connected to the sense amplifier array input/output lines, reducing overall current consumption.

Abstract: The wordline driving circuit includes a noise prevention circuit in each control circuit of a subwordline drive selector. When a row signal from a sub-row decoder indicates that the associated control circuits are not to drive wordlines associated therewith, the noise prevention circuit in each control circuit is triggered to remove noise from the wordline.

Abstract: The present invention relates to a charge pump circuit for memory device, more particularly to a circuit charging cell capacitors or bitlines up to a full level of power supply voltage by means of compensating for the loss caused by the threshold voltages of memory transistors with the elevated potential higher than the power supply voltage.

Abstract: A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends.

Abstract: A word line driving circuit for a semiconductor memory is provided that drives a corresponding word line of a first number of word lines coupled to a plurality of memory cells based on a memory address signal generated from a more significant controller. The memory cells have a matrix form of rows and columns and the first number of word lines are divided into a second number of word line groups. The word line driving circuit includes a second number of word line group driving circuits each respectively coupled to one of the second number of word line groups to drive one of the word lines in the word line group selected by a control signal. A word line selecting circuit determines which of the second word line groups contain the corresponding word line to be driven using the memory address signal and generates the control signal for the corresponding word line group driving circuit.

Abstract: A semiconductor device is provided having a symmetric bitline precharge circuit. Sizes of a parasitic devices near transistors lying symmetrically in the bitline precharge circuit are symmetrical to each other. Further, a layout area occupied by the bitline precharge circuit or a chip is reduced or minimized by the symmetric layout. The device can include a memory having first and second bitline extending in parallel a first direction a bitline precharge voltage supplying line and a bitline equalizing signal line extending in parallel in a second direction perpendicular to the first direction. A gate has at least a first part extending in the first direction, a second part having a first predetermined length extending in the second direction coupled to the first part and a third part having a second predetermined length extending in the second direction coupled to the first part with contact areas at uncoupled ends.