Patents by Inventor Chang-Ming Hsieh
Chang-Ming Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937903Abstract: A blood pressure device includes a first blood pressure measuring device, a second blood pressure measuring device, and a controller. The first blood pressure measuring device is to be worn on a first position of a wrist so as to obtain a first blood pressure information of the first position. The second blood pressure measuring device is to be worn on a second position of the wrist so as to obtain a second blood pressure information of the second position. The controller is electrically coupled to the first blood pressure measuring device and the second blood pressure measuring device so as to adjust tightness between the expanders and the user's skin, respectively. The controller receives, processes, and calculates a pulse transit time between the first blood pressure information and the second blood pressure information, and the controller obtains at least one blood pressure value based on the pulse transit time.Type: GrantFiled: December 29, 2020Date of Patent: March 26, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Chin-Wen Hsieh
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Publication number: 20230210642Abstract: An intraoral scanning system is described herein. The intraoral scanning system includes a scanning device and a processing device. The scanning device is configured to illuminate an object of interest with a burst light pattern at one or more intervals and receive a set of reflected images reflected off the object of interest. The processing device is configured to receive the set of reflected images from the scanning device and convert the set of reflected images into a three-dimensional model of the object of interest. The burst light pattern comprises a first image and a second image in succession. One of the first image and the second image is a structured light image and the other of the first image and the second image is an unstructured light image.Type: ApplicationFiled: December 30, 2022Publication date: July 6, 2023Applicant: MEDIT CORP.Inventors: Saradwata SARKAR, Mark GREENWOOD, Mark Chang-Ming HSIEH, James Lee ONSLOW
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Patent number: 8935110Abstract: A system for analyzing an interior energy system including: at least one detachable sensor arranged to monitor a portion of the interior energy system; and an apparatus including a processor configured to receive data of a first parameter of the interior energy system from the at least one detachable sensor and determine a second parameter of the interior energy which is inferred on the basis of the received data of the first parameter; and determine a characteristic of the interior energy system from the determined second parameter. The system may provide analysis of the interior energy system and recommend improvements.Type: GrantFiled: October 26, 2009Date of Patent: January 13, 2015Assignee: The Technology Partnership PLCInventors: Mark Chang-Ming Hsieh, David Russell Anderson
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Publication number: 20110276288Abstract: A system for analysing an interior energy system comprising: at least one detachable sensor arranged to monitor a portion of the interior energy system; and an apparatus comprising a processor configured to receive data of a first parameter of the interior energy system from the at least one detachable sensor and determine a second parameter of the interior energy which is inferred on the basis of the received data of the first parameter; and determine a characteristic of the interior energy system from the determined second parameter. The system may provide analysis of the interior energy system and recommend improvements.Type: ApplicationFiled: October 26, 2009Publication date: November 10, 2011Inventors: Mark Chang-Ming Hsieh, David Russell Anderson
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Patent number: 6144081Abstract: A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.Type: GrantFiled: October 11, 1995Date of Patent: November 7, 2000Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Chang-Ming Hsieh, Lyndon Ronald Logan, Jack Allan Mandelman, Seiki Ogura
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Patent number: 6107141Abstract: An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.Type: GrantFiled: September 29, 1998Date of Patent: August 22, 2000Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Chang-Ming Hsieh, Seiki Ogura
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Patent number: 5962895Abstract: SOI Transistor Having a Self-aligned Body Contact An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.Type: GrantFiled: November 10, 1994Date of Patent: October 5, 1999Assignee: International Business Machines CorporationInventors: Klaus Dietrich Beyer, Taqi Nasser Buti, Chang-Ming Hsieh, Louis Lu-Chen Hsu
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Patent number: 5910912Abstract: An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.Type: GrantFiled: October 30, 1992Date of Patent: June 8, 1999Assignee: International Business Machines CorporationInventors: Louis Lu-Chen Hsu, Chang-Ming Hsieh, Seiki Ogura
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Patent number: 5874764Abstract: An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.Type: GrantFiled: July 24, 1996Date of Patent: February 23, 1999Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Shao-Fu Sanford Chu, Louis Lu-chen Hsu
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Patent number: 5774411Abstract: Modifications of a digital logic device, such as a static or dynamic random access memory (SRAM or DRAM) or pass gate logic circuit or the like, implemented with complementary metal-oxide-semiconductor (CMOS) structures formed with silicon-on-insulator (SOI or, more specifically, SOICMOS) technology effectively suppress transient parasitic bipolar current disturbances (e.g. transient half select write disturb instabilities) caused by a discharge current through a parasitic lateral bipolar transistor formed under the transfer gate field effect transistors. Level shifting of the "off" voltage applied to the gate electrode of the transfer gate transistor dynamically changes the gain of the cell transfer gate to increase memory cell stability without compromising the memory capacity per chip or read/write memory cycle time even though level shifting can greatly increase majority carrier density in the floating body (gate) of a SOICMOS transistor at a particular level shifted voltage range.Type: GrantFiled: September 12, 1996Date of Patent: June 30, 1998Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Louis L. Hsu, Jack A. Mandelman, Mario M. A. Pelella
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Patent number: 5729039Abstract: An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.Type: GrantFiled: May 3, 1996Date of Patent: March 17, 1998Assignee: International Business Machines CorporationInventors: Klaus Dietrich Beyer, Taqi Nasser Buti, Chang-Ming Hsieh, Louis Lu-Chen Hsu
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Patent number: 5721144Abstract: An improved design for high aspect ratio MOS devices is capable of 100% yields. The design is suitable for low voltage CMOS devices, such as microprocessors, which use the high aspect ratio MOS devices in embedded applications, and for HEMTs in high frequency applications, such as high power microwave devices. The high yields reduce manufacturing costs. A modular MOS concept is introduced to realize the 100% yield of large channel width devices. The structure of the modular MOS device is a regular MOS device with a unit device channel width. This can be a multi-finger device which has a proper dimension to be able to fit in a given layout area. Therefore, the number of modules which are needed to form a full large width device is not only determined by module size, but also on the manufacturing yield record, allowed chip real estate and performance requirement.Type: GrantFiled: October 24, 1995Date of Patent: February 24, 1998Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Somnuk Ratanaphanyarat, Shao-Fu Sanford Chu, Louis Lu-chen Hsu
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Patent number: 5567553Abstract: A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.Type: GrantFiled: May 18, 1995Date of Patent: October 22, 1996Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Chang-Ming Hsieh, Lyndon R. Logan
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Patent number: 5528062Abstract: A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.Type: GrantFiled: June 17, 1992Date of Patent: June 18, 1996Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Louis L. C. Hsu, Seiki Ogura
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Patent number: 5521399Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.Type: GrantFiled: May 16, 1994Date of Patent: May 28, 1996Assignee: International Business Machines CorporationInventors: Shao-Fu S. Chu, Chang-Ming Hsieh, Louis L. C. Hsu, Kyong-Min Kim, Shaw-Ning Mei
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Patent number: 5484738Abstract: A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.Type: GrantFiled: March 1, 1995Date of Patent: January 16, 1996Assignee: International business Machines CorporationInventors: Shao-Fu S. Chu, Chang-Ming Hsieh, Louis L. C. Hsu, Kyong-Min Kim, Shaw-Ning Mei
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Patent number: 5466625Abstract: A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.Type: GrantFiled: November 22, 1994Date of Patent: November 14, 1995Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Louis L. C. Hsu, Seiki Ogura
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Patent number: 5446312Abstract: A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.Type: GrantFiled: June 24, 1994Date of Patent: August 29, 1995Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Louis L. G. Hsu, Shaw-Ning Mei, Ronald W. Knepper, Lawrence F. Wagner, Jr.
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Patent number: 5405795Abstract: An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.Type: GrantFiled: June 29, 1994Date of Patent: April 11, 1995Assignee: International Business Machines CorporationInventors: Klaus D. Beyer, Taqi N. Buti, Chang-Ming Hsieh, Louis L. Hsu
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Patent number: 5389559Abstract: A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell.Type: GrantFiled: December 2, 1993Date of Patent: February 14, 1995Assignee: International Business Machines CorporationInventors: Chang-Ming Hsieh, Louis L. Hsu, Toshio Mii, Seiki Ogura, Joseph F. Shepard