Patents by Inventor Chang-Mo Yoo

Chang-Mo Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8183070
    Abstract: A method of fabricating an array substrate for a liquid crystal display device includes: forming an initial photoresist (PR) pattern on a metallic material layer; etching the metallic material layer using the initial PR pattern as an etching mask to form the data line and a metallic material pattern, wherein the initial PR pattern is disposed on the data line; performing a first ashing process onto the initial PR pattern to partially remove the initial PR pattern so as to form a first ashed PR pattern, the first ashed PR pattern having a smaller width and a smaller thickness than the initial PR pattern such that end portions of the data line are exposed by the first ashed PR pattern; etching the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer by a first dry-etching process; forming a source electrode and a drain electrode on the substrate.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: May 22, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Seok-Won Kim, Won-Joon Ho, Hyuk-Jin Kwon, Chang-Mo Yoo
  • Publication number: 20090294781
    Abstract: A method of fabricating an array substrate for a liquid crystal display device includes: forming an initial photoresist (PR) pattern on a metallic material layer; etching the metallic material layer using the initial PR pattern as an etching mask to form the data line and a metallic material pattern, wherein the initial PR pattern is disposed on the data line; performing a first ashing process onto the initial PR pattern to partially remove the initial PR pattern so as to form a first ashed PR pattern, the first ashed PR pattern having a smaller width and a smaller thickness than the initial PR pattern such that end portions of the data line are exposed by the first ashed PR pattern; etching the intrinsic amorphous silicon layer and the impurity-doped amorphous silicon layer by a first dry-etching process; forming a source electrode and a drain electrode on the substrate.
    Type: Application
    Filed: November 14, 2008
    Publication date: December 3, 2009
    Inventors: Seok-Won KIM, Won-Joon Ho, Hyuk-Jin Kwon, Chang-Mo Yoo