Abstract: The present disclosure provides a device and method for depth sensing by utilizing the combination of a ranging sensor and an image sensor. The ranging sensor can accurately detect distance measurement from an object. The image sensor can take images with high resolution of the object. By combining each sensor data from the ranging sensor and the image sensor, accurate depth information with high resolution of the object may be obtained. A structured light having patterned shapes are used in conjunction with the ranging sensor to receive reflected patterned shapes of the object. These reflected patterned shapes are used to analyze distance measurements associated with the specific patterned shapes. These distance measurements from both the ranging sensor and the image sensor is aligned and combined to generate an accurate depth map with high resolution using a processor of an electronic device including the ranging sensor and the image sensor.

Abstract: The present disclosure provides a device and method for depth sensing by utilizing the combination of a ranging sensor and an image sensor. The ranging sensor can accurately detect distance measurement from an object. The image sensor can take images with high resolution of the object. By combining each sensor data from the ranging sensor and the image sensor, accurate depth information with high resolution of the object may be obtained. A structured light having patterned shapes are used in conjunction with the ranging sensor to receive reflected patterned shapes of the object. These reflected patterned shapes are used to analyze distance measurements associated with the specific patterned shapes. These distance measurements from both the ranging sensor and the image sensor is aligned and combined to generate an accurate depth map with high resolution using a processor of an electronic device including the ranging sensor and the image sensor.

Abstract: A method and apparatus for determining space occupancy and performing volumetric measurement of a transportation system using a time-of-flight (TOF) sensor array are provided. In the method and apparatus, the TOF sensor array, which is mounted in a transportation system and includes a plurality of TOF sensors, outputs a plurality of distance measurements made by the plurality of TOF sensors, respectively. In the method and apparatus, a map of one or more objects positioned in the transportation system is generated based on the plurality of distance measurements. The map is output for display to a user by a display.

Abstract: A method and apparatus for determining space occupancy and performing volumetric measurement of a transportation system using a time-of-flight (TOF) sensor array are provided. In the method and apparatus, the TOF sensor array, which is mounted in a transportation system and includes a plurality of TOF sensors, outputs a plurality of distance measurements made by the plurality of TOF sensors, respectively. In the method and apparatus, a map of one or more objects positioned in the transportation system is generated based on the plurality of distance measurements. The map is output for display to a user by a display.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: Disclosed is a PCB including an embedded capacitor and a method of fabricating the same. The long embedded capacitor is formed through an insulating layer, making a high capacitance and various capacitance designs possible.

Abstract: An interconnection element can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts may overlie and project away from respective ones of the conductive elements. An intermetallic layer can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts and the conductive elements. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer.

Abstract: A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

Abstract: A high frequency signal transmission line having reduced noise. Particularly, a signal transmission line of the current invention has reduced radiation noise and reflection noise, because a conventional ground guard fence line disposed between signal lines is separated into a plurality of ground line blocks that are spaced apart from each other to shield against noise.

Abstract: Disclosed is a PCB including an embedded capacitor and a method of fabricating the same. The long embedded capacitor is formed through an insulating layer, making a high capacitance and various capacitance designs possible.

Abstract: Disclosed is a PCB including an embedded capacitor and a method of fabricating the same. The long embedded capacitor is formed through an insulating layer, making a high capacitance and various capacitance designs possible.

Abstract: Disclosed is a PCB having axially parallel via holes, in which an outer ground via hole, acting as a ground, is formed around a via hole for intercircuit connection in the PCB, thereby minimizing the effect of noise caused by the via hole.

Abstract: The present invention relates to a capacitor-embedded PCB and a method of manufacturing the same. The capacitor-embedded PCB includes a dielectric layer, a lower electrode layer formed under the dielectric layer, and an upper electrode layer formed on the dielectric layer and configured to have at least one first blind via hole that is inwardly formed.

Abstract: A printed circuit board (PCB) having a three-dimensional spiral inductor, which includes a plurality of insulating layers and conductor layers. The PCB comprises a plurality of coil conductor patterns made of conductive material and shaped into strips, which is provided on the plurality of conductor layers, respectively, such that the plurality of coil conductor patterns are parallel to each other and positioned on the same plane perpendicular to the conductor layers, and in which each of the plurality of coil conductor patterns is longer than an adjacent inner coil conductor pattern.