Abstract: A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region.

Abstract: A sputtering target apparatus is provided. The sputtering target apparatus includes a first target assembly including a first target array having a first target, a second target disposed adjacent to the first target, and a first target dividing region disposed between the first and second targets, the first target assembly extending along a first direction, wherein the first target dividing region has a longitudinal cross-section that is oblique with respect to the first direction.

Abstract: A liquid crystal display includes: a substrate; a thin film transistor on the substrate; a pixel electrode which is connected to a terminal of the thin film transistor; a microcavity layer on the pixel electrode and including an injection hole through which material is provided to the microcavity layer; a supporting layer on the microcavity layer; and a capping layer on the supporting layer. The capping layer covers the injection hole, and the supporting layer includes silicon oxycarbide (SiOC).

Abstract: A method of fabricating a thin-film transistor (TFT) substrate includes forming a gate electrode on a substrate; forming an insulating film on the gate electrode; forming an amorphous semiconductor pattern on the insulating film; and forming a source electrode separated from a drain electrode on the amorphous semiconductor pattern; forming a light-concentrating layer, which includes a protrusion, on the amorphous semiconductor pattern, the source electrode, and the drain electrode; and crystallizing at least part of the amorphous semiconductor pattern by irradiating light to the protrusion of the light-concentrating layer.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including a copper layer and a copper solid solution layer.

Abstract: A method for manufacturing a display panel includes; formation of a lower gate line, disposal of a semiconductor on the lower gate line, disposal of a lower data line substantially perpendicular to the lower gate line, disposal of an insulating layer having a plurality of trenches exposing the lower gate line and the lower data line on the lower data line, disposal of an upper gate line directly on the lower gate line and within the plurality of trenches, and disposal of an upper data line directly on the lower data line and within the plurality of trenches.

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract: A thin film transistor array panel includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a gate insulating layer disposed on the gate line; an semiconductive oxide layer disposed on the gate insulating layer; a data line disposed on the semiconductive oxide layer and including a source electrode; a drain electrode facing the source electrode on the semiconductive oxide layer; and a passivation layer disposed on the data line. The semiconductive oxide layer is patterned with chlorine (Cl) containing gas which alters relative atomic concentrations of primary semiconductive characteristic-providing elements of the semiconductive oxide layer at least at a portion where a transistor channel region is defined.

Abstract: A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

Abstract: A thin film transistor array panel is provided, which includes a plurality of gate lines, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.

Abstract: Provided are a thin-film transistor (TFT) substrate and a method of manufacturing the same. The method includes: forming a passivation film by forming an insulating film on a substrate; forming a photoresist pattern by forming a photoresist film on the passivation film, exposing the photoresist film to light, and developing the photoresist film; performing a first dry-etching by dry-etching the passivation film using the photoresist pattern as an etch mask; performing a baking to reduce a size of the photoresist pattern; performing a second dry-etching to form a contact hole by dry-etching the passivation film again using the photoresist pattern as a mask; removing the photoresist pattern; and forming a pixel electrode of a carbon composition that includes carbon nanotubes and/or graphene on a top surface of the passivation film.

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Abstract: A thin film transistor array panel is provided, which includes a plurality of gate line, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.

Abstract: A liquid crystal display (LCD) includes thin film transistors (TFTs) each having spaced apart source/drain electrodes and an oxide-type semiconductive film disposed over and between the source/drain electrodes to define an active layer. Each of the source/drain electrodes includes a portion of a subdivided transparent conductive layer where one subdivision of the transparent conductive layer continues from within its one of the source/drain electrodes to define an optically exposed pixel-electrode that is reliably connected integrally to the one source/drain electrode. Mass production costs can be reduced and production reliability increased because a fewer number of photolithographic masks can be used to form the TFTs.

Abstract: A thin film transistor includes a gate electrode on a substrate, a main active layer in electrical connection with the gate electrode and including an exposed channel portion, a source electrode in electrical connection with the main active layer, a drain electrode which is spaced apart from the source electrode and in electrical connection with the main active layer, and a sub active layer in electrical connection to the main active layer.

Abstract: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes.

Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.

Abstract: The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

Abstract: A thin film transistor array panel includes: an substrate; a gate line positioned on the substrate; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a gate insulating layer between the gate electrode of the thin film transistor and the semiconductor of the thin film transistor; a pixel electrode connected to the thin film transistor; and a passivation layer positioned between the pixel electrode and the thin film transistor, wherein at least one of the gate insulating layer and the passivation layer includes a silicon nitride layer, and the silicon nitride layer includes hydrogen content at less than 2×1022 cm3 or 4 atomic %.

Abstract: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes.