Abstract: Titanium is deposited using a low-pressure chemical-vapor deposition to provide good step coverage over an underlying integrated circuit structure. A rapid thermal anneal is performed using an ambient including diborane. The rapid thermal anneal causes the titanium to interact with underlying silicon to form titanium silicide. Concurrently, the diborane reacts with the titanium to form titanium boride. A composite barrier layer results. Aluminum is deposited and then patterned together with the composite barrier layer to define a first level metalization. Subsequent intermetal dielectrics, metalization, and passivation layers can be added to form a multi-level metal interconnect structure. The titanium boride prevents the aluminum from migrating into the silicon, while the titanium silicide lowers the contact resistivity associated with the barrier layer. The relatively close match of the thermal coefficients of expansion for titanium boride and silicon provides high thermal stability.

Abstract: An improved anneal process is disclosed for use in the preparation of a dielectric layer, especially an intermetal dielectric layer. An oxide layer is deposited using a H.sub.2 O-TEOS PECVD process. A vacuum bake is used to minimize or eliminate volatile water, hydrogen, and hydrocarbon impurities in the dielectric layer. An oxidation anneal is then performed to scavenge any remaining undesirable species, and to provide for densification of the dielectric layer.

Abstract: A titanium-tungsten barrier layer is sputtered after active areas of a CMOS structure are exposed. An ion implant through the barrier layer and into the active areas disrupts the boundaries between the barrier layer and the underlying active areas. The implant can involve argon or, alternatively, silicon. The resulting structure is annealed. A conductor layer of an aluminum-copper alloy is deposited. An antireflection coating of TiW is deposited. The three-layer structure is then photolithographically patterned to define contacts and local interconnects. The ion implant before anneal results in less contact resistance, which is particularly critical for the barrier layer boundary with positively doped active areas.

Abstract: A method of metalization of semiconductor devices wherein predominantly aluminum metal films incorporate a minor amount of magnesium in admixture with the aluminum, or in layered juxtaposition with the aluminum layer, to provide resistance to corrosion, particularly acidic corrosion.

Abstract: A dry etcher and method using two chambers can be used for anisotropic or isotropic etching. A pressure differential is created between the first and second chambers using a passage between the first and second chambers. Additionally, baffles which remove some of the ions created in the first chamber are used.

Abstract: Increases in the contact resistance at the aluminum-silicon interface in contact points is inhibited by employing a molybdenum boride conductive barrier layer between the aluminum conductor and the silicon substrate.

Abstract: Disclosed are methods for preparing SiO.sub.2 layers in semiconductor devices by the rapid thermal oxidation of silicon in an ozone ambient.

Abstract: A semiconductor processing method provides for plasma-enhanced chemical-vapor deposition (PECVD) for intermetal dielectrics while minimizing risk of gate oxide impairment due to plasma discharge. A protective oxide sublayer is deposited without using high-power PECVD. The protective sublayer can be deposited by using chemical-vapor deposition (CVD) without plasma enhancement or by a lower-power PECVD. In the latter case, the initial rf power of the plasma is selected to be low enough to ensure that the gate oxide is not breached in the event of a plasma discharge. The protective sublayer can be thick enough to maintain its integrity in the event of a plasma discharge even during a higher-power PECVD deposition.