Abstract: A panel display apparatus and a method for driving the display panel are provided. The panel display apparatus includes a display panel and a plurality of source drivers. The display panel with X*Y display unit includes X+1 data lines, and each source driver has M+1 data output terminals DOi,j. In addition, each of the data output terminals of the source drivers is electrically coupled to a corresponding data line of the display panel, respectively. The mentioned DOi,j represents the jth data output terminal of the ith source driver. Wherein, the data output terminal DOi,M and the data output terminal DOi+1,0 are electrically coupled to a same data line of the display panel.

Abstract: A method capable of reducing power consumption of source drivers is disclosed. The method includes a reference voltage source charging or discharging a loading end of a source driver to a reference voltage having a polarity the same as a polarity of a target voltage and a voltage level near a voltage level of the target voltage, and an output stage of the source driver charging or discharging the loading end to the target voltage.

Abstract: A display panel is disclosed. The display units with the same position at odd rows and even rows are electrically coupled to different data lines, such that most of the time each of the data lines on the display panel is maintained on a single polarity, respectively. Accordingly, the swing voltage of the data lines on the display panel is reduced when scanning an image, such that the power consumption of the display panel is further reduced in order to achieve the object of saving power.

Abstract: An LCD includes a display panel, a source driver, a gate driver, a timing controller, and a data converter. The display panel includes a plurality of pixel units, and each pixel unit has three sub-pixels. Each pixel is driven according to one or two data lines. The sub-pixels of the display panel are arranged to improve the display effect. The data converter converts the image data to drive the display panel.

Abstract: A data switching circuit is provided, which reduces power consumption of the source drivers when used together with a dot inversion driving method. The circuit comprises a control unit and a switching unit. Wherein, the control unit provides a switching signal. The switching unit has 2N input terminals and 2N output terminals and receives the switching signal. Assume that N is a positive integer and 1?i?N. When the switching signal is in a first state, the switching unit connects the (2i?1)th input terminal and the (2i?1)th output terminal, and connects the 2ith input terminal and the 2ith output terminal. When the switching signal is in a second state, the switching unit connects the 2ith input terminal and the (2i?1)th output terminal, and connects the (2i?1)th input terminal and the 2ith output terminal.

Abstract: A data switching circuit is provided. The circuit includes a control unit and a switching unit. The control unit provides a switching signal. The switching unit has N input ends and (N+1) output ends. The switching unit receives the switching signal. If N is an integer number and 1?i?N, the switching unit turns on both the connection between the i-th input end and the i-th output end and the connection between a dummy data and the (N+1) output end as the switching signal takes a first status. The switching unit turns on both the connection between another set of dummy data and the first output end and the connection between the i-th input end and the (i+1)-th output end as the switching signal takes a second status.

Abstract: A source driver and an internal data transmission method are provided. The present invention employs specially designed switch units and creates specially designed data paths in a source driver, which matches with the driving method for dot invesion and the specially designed pixel array. When the dot inversion driving method is used on a pixel array of a specific design, each output buffer and digital-to-analog converter inside the source driver continuously output voltages of positive polarity and voltages of negative polarity, instead of switching between positive and negative polarities. Consequently, the swing voltages that the source driver outputs can be lowered, the power consumption can also be reduced accordingly, a smaller area is occupied, and the costs are reduced.

Abstract: A charge pump clock generating circuit and a method thereof are disclosed. The circuit includes a sync counter, a comparator, and a clock generating circuit. The sync counter receives a dot clock and a reset signal for accumulating a counting value according to the dot clock and resetting the counting value to a starting value when the reset signal is enabled. The comparator receives the counting value and outputs the reset signal when the counting value is greater than or equal to a preset value. The clock generating circuit receives a display clock and the reset signal and outputs a charge pump clock. The clock generating circuit transforms the logic state of the charge pump clock when the reset signal is enabled, and sets the charge pump clock to a first preset logic state when the display clock is transformed from a first state to a second state.

Abstract: A charge pump clock generating circuit and a method thereof are disclosed. The circuit includes a sync counter, a comparator, and a clock generating circuit. The sync counter receives a dot clock and a reset signal for accumulating a counting value according to the dot clock and resetting the counting value to a starting value when the reset signal is enabled. The comparator receives the counting value and outputs the reset signal when the counting value is greater than or equal to a preset value. The clock generating circuit receives a display clock and the reset signal and outputs a charge pump clock. The clock generating circuit transforms the logic state of the charge pump clock when the reset signal is enabled, and sets the charge pump clock to a first preset logic state when the display clock is transformed from a first state to a second state.

Abstract: A Gamma reference voltage generating device related to a liquid crystal display is provided. The device comprises a voltage dividing device and multiple voltage followers. The voltage dividing device provided multiple voltage dividing signals comprises multiple voltage dividing elements (usually resisters or capacitors) connected in series. An optional image data processing operational amplifier, also referred as dummy or repair OP-AMP, in each data driver ICs is utilized as a voltage follower to receive one of the above voltage dividing signals and output a Gamma reference voltage respectively. An optional image data processing operational amplifier in the data driver integrated circuit is utilized according to the present invention, such that the amount of operational amplifier ICs that is required is significantly reduced. Thus, the circuit cost and the power consumption are effectively reduced, as well as the area of the printed circuit board.

Abstract: A method capable of reducing power consumption of source drivers is disclosed. The method includes a reference voltage source charging or discharging a loading end of a source driver to a reference voltage having a polarity the same as a polarity of a target voltage and a voltage level near a voltage level of the target voltage, and an output stage of the source driver charging or discharging the loading end to the target voltage.

Abstract: A pixel matrix used in a liquid crystal display, including a plurality of pixel units. Each pixel unit includes a storage unit, a first switch and a second switch. The storage unit determines the displayed gray scale of the pixel unit according to a pixel voltage applied to the storage unit. The first switch is coupled between a first data line, a first scan line and the storage unit. The first switch connects or disconnects the first data line with the storage unit, according to the state of the signal on the first scan line. On the other hand, the second switch is coupled between a second data line, a second scan line and the storage unit. The second switch connects or disconnects the second data line with the storage unit, according to the state of the signal on the second scan line.

Abstract: A data switching circuit is provided. The circuit includes a control unit and a switching unit. The control unit provides a switching signal. The switching unit has N input ends and (N+1) output ends. The switching unit receives the switching signal. If N is an integer number and 1?i?N, the switching unit turns on both the connection between the i-th input end and the i-th output end and the connection between a dummy data and the (N+1) output end as the switching signal takes a first status. The switching unit turns on both the connection between another set of dummy data and the first output end and the connection between the i-th input end and the (i+1)-th output end as the switching signal takes a second status.

Abstract: A data switching circuit is provided, which reduces power consumption of the source drivers when used together with a dot inversion driving method. The circuit comprises a control unit and a switching unit. Wherein, the control unit provides a switching signal. The switching unit has 2N input terminals and 2N output terminals and receives the switching signal. Assume that N is a positive integer and 1?i?N. When the switching signal is in a first state, the switching unit connects the (2i?1)th input terminal and the (2i?1)th output terminal, and connects the 2ith input terminal and the 2ith output terminal. When the switching signal is in a second state, the switching unit connects the 2ith input terminal and the (2i?1)th output terminal, and connects the (2i?1)th input terminal and the 2ith output terminal.

Abstract: A source driver and an internal data transmission method are provided. The present invention employs specially designed switch units and creates specially designed data paths in a source driver, which matches with the driving method for dot invesion and the specially designed pixel array. When the dot inversion driving method is used on a pixel array of a specific design, each output buffer and digital-to-analog converter inside the source driver continuously output voltages of positive polarity and voltages of negative polarity, instead of switching between positive and negative polarities. Consequently, the swing voltages that the source driver outputs can be lowered, the power consumption can also be reduced accordingly, a smaller area is occupied, and the costs are reduced.

Abstract: A panel display apparatus and a method for driving the display panel are provided. The panel display apparatus includes a display panel and a plurality of source drivers. The display panel with X*Y display unit includes X+1 data lines, and each source driver has M+1 data output terminals DOi,j. In addition, each of the data output terminals of the source drivers is electrically coupled to a corresponding data line of the display panel, respectively. The mentioned DOi,j represents the jth data output terminal of the ith source driver. Wherein, the data output terminal DOi,M and the data output terminal DOi+1,0 are electrically coupled to a same data line of the display panel.

Abstract: A display panel is disclosed. The display units with the same position at odd rows and even rows are electrically coupled to different data lines, such that most of the time each of the data lines on the display panel is maintained on a single polarity, respectively. Accordingly, the swing voltage of the data lines on the display panel is reduced when scanning an image, such that the power consumption of the display panel is further reduced in order to achieve the object of saving power.

Abstract: An apparatus and method for demodulating a frequency-shift keyed (FSK) signal to provide a data signal. An input FSK signal is processed in a waveform reshaper to generate a first pulse signal which includes a pulse for each cycle of the FSK signal. The first pulse signal is processed in a cycle counter to generate second and third pulse signals. The second pulse signal includes a pulse for each time a low clock pulse count is reached between pulses of the first pulse signal, and the third pulse signal includes a pulse for each time a high clock pulse count is reached between pulses of the first pulse signal. The low and high pulse counts are generally indicative of cycles of first and second FSK carrier frequencies, respectively, in the input FSK signal. The second pulse signal is processed in a data recognizer to generate a logic level indicator signal.

Abstract: A programmable multi-level bus arbitration apparatus for computer systems which implements dynamic arbitration for the grant of control over a system bus by one of a number of bus master devices. A number of programmable restricters each receive a system bus request signal issued by a corresponding one of the bus master devices competing for the control over the system bus. The restricters block or relay the bus request signal. A programmable priority arbiter receives an output of each of the restricters for arbitration to grant control of the system bus to a selected one of the bus master devices based on a pre-programmed priority scheme. A communication protocol handler receives and monitors the status of the bus enable signal for generating a bus busy signal to control the issuing of a verified bus request signal by one of the restricters or the blocking of the bus request signal based on the status of the bus busy signal.