Abstract: Disclosed is a tire curing mould with internal holes including a plurality of segment moulds disposed in a circumferential direction of a tire and assembled to each other, and a plurality of holes formed through the segment moulds, characterized in that each of the segment moulds 100 has a through hole 110 formed in a circumferential direction of the segment mould 100, whereby it is possible to provide a high quality tire which is lightweight and easy to maintain, and has excellent durability and high heat transfer efficiency.

Abstract: The present invention relates to a method of manufacturing a built-in type upper/lower electrode multi-layer part including alternately laminating a first ceramic sheet having a first internal electrode pattern formed thereon and a second ceramic sheet having a second internal electrode pattern formed thereon so as to form a first multi-layer sheet product; forming first and second via holes on the first multi-layer sheet product, the first and second via holes respectively connecting the first and second internal electrode patterns; respectively joining third and fourth ceramic sheets having no internal electrode pattern on the upper and lower portions of the first multi-layer sheet product so as to form a second multi-layer sheet product, the third and fourth ceramic sheets having third and fourth via holes formed to correspond to the first and second via holes; and filling a conductive paste in the first to fourth via holes.

Abstract: A grinder wheel for a liquid crystal display device and a method of fabricating a liquid crystal display device using the same are provided. Two grinding surfaces are formed in the grinder wheel used for grinding a substrate so that it is possible to improve grinding characteristics, to increase the life of the grinder wheel, and to reduce grinding time. The method includes cutting the substrates attached to each other into a plurality of unit liquid crystal display panels, loading the unit liquid crystal display panel on a grinding table, grinding a predetermined region of the liquid crystal display panel using a grinder wheel including two grinding surfaces of a first grinder surface for primary grinding and a second grinder surface for secondary grinding, and unloading the ground liquid crystal display panel.

Abstract: The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.

Abstract: A display apparatus includes a display panel, a light guiding unit, a main flexible printed circuit board (FPC) and a sub FPC. The light guiding unit is disposed adjacent to a first side of the display panel. The main FPC is electrically connected to a second side of the display panel to apply an electrical signal to the display panel. The sub FPC is electrically connected to the main FPC. A light emitting device generates light supplied to the light guiding unit, and is mounted on the sub FPC.

Abstract: The invention provides an embedded multilayer chip capacitor, and a printed circuit board having the same. The embedded multilayer chip capacitor comprises a capacitor body having a plurality of dielectric layers stacked one on another; a plurality of first and second internal electrodes formed inside the capacitor body, separated by the dielectric layers; and first and second vias extended vertically inside the capacitor body. The first via is connected to the first internal electrodes and the second via is connected to the second internal electrodes. The first via is led to a bottom of the capacitor body and the second via is led to a top of the capacitor body.

Abstract: A multilayer chip capacitor, which reduces ESL generated due to current flowing through external electrodes and assures an improved mechanical strength. The multilayer chip capacitor includes an upper dummy layer and a lower dummy layer; a plurality of internal electrodes interposed between the upper and lower dummy layers; and external electrodes connected to the internal electrodes, wherein the thickness of the lower dummy layer is smaller than the thickness of the upper dummy layer.

Abstract: The present invention provides a multilayered chip capacitor (MLCC) comprising internal electrodes and external electrodes formed to be perpendicular to the internal electrodes, whereby parasitic capacitance is reduced, resulting in no parallel resonance frequency effects. In addition, the MLCC has a capacitor structure, which provides a first surface and a second surface formed in a stacking direction of the dielectric layers in the capacitor body as a top surface and a bottom surface. Hence, in the thin capacitors having the same size, the number of internal electrode layers is increased, thereby reducing the ESR and ESL. Further, the PCB having an embedded MLCC is easily manufactured.

Abstract: A multi-layer chip capacitor comprises a capacitor body formed by stacking a plurality of dielectric layers; a plurality of first and second internal electrodes formed on the dielectric layers, each having at least one through hole formed through at least one side thereof; lowermost electrode patterns, each including a lead portion extended to one side of the capacitor body, and a via contact portion; a plurality of conductive vias, vertically extended to pass through the through holes so as not to contact the inner surfaces of the through holes, each of the contact vias connected to either the first or second internal electrode and contacting the via contact portion; and a plurality of terminal electrodes formed on the outer surface of the capacitor body, and connected to the conductive vias through the lead portions.

Abstract: Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.

Abstract: In a driving unit and a display apparatus, a master driving chip includes a common voltage generator configured to receive power and generate a master common voltage and a slave common voltage and a first data driver configured to output a master image signal based on the master common voltage and a master data signal. A slave driving chip includes a second data driver configured to output a slave image signal based on the slave common voltage from the common voltage generator and a slave data signal. Accordingly, the malfunction of the driving unit and the display apparatus may be prevented.

Abstract: A laminated ceramic capacitor includes a ceramic block formed by laminating a plurality of ceramic sheets, a plurality of external electrodes formed on outer surfaces of the ceramic block facing each other, and set as a positive terminal and a negative terminal, respectively, one or more first and second internal electrodes alternately arranged within the ceramic block such that electric currents flow in opposite directions in the internal electrodes, and a plurality of withdrawing patterns for connecting the first and second internal electrodes to the external electrodes, respectively.