Abstract: A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

Abstract: A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

Abstract: An element-selecting method is utilized for selecting the converting elements of the DAC to perform the digital-to-analog conversion. The element-selecting method first determines whether the selected times of the converting elements are all equal or not. When the selected times of the converting elements are all equal, the element-selecting method determines a shifting-step according to the input signal and the number of the converting elements; otherwise, the element-selecting method determines the shifting-step to be a predetermined value. The element-selecting method then selects a converting element from the DAC by means of separating the converting element from a last selected converting element by the shifting-step. In this way, the error accumulated because of the mismatch of the converting elements is eliminated, and the toggle rate of the DAC is reduced. Hence, the glitch and the dynamic errors of the DAC are reduced, improving the performance of the DAC.

Abstract: A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

Abstract: A method for reducing current consumption of digital-to-analog conversion includes: monitoring logical states of a set of differential digital inputs, wherein the set of differential digital inputs are utilized for controlling at least one tri-state current Digital-to-Analog Converter (DAC) cell of a tri-state current DAC, and the tri-state current DAC cell has a positive output current state, a zero output current state and a negative output current state; and when the logical states of the set of differential digital inputs instruct the tri-state current DAC cell should output no positive/negative current, controlling the tri-state current DAC cell to switch to the zero output current state, temporarily decreasing a direct current passing through a middle path of the tri-state current DAC cell. An associated tri-state current DAC is also provided, where the tri-state current DAC includes: the at least one tri-state current DAC cell; and a control device.

Abstract: A method for reducing current consumption of digital-to-analog conversion includes: monitoring logical states of a set of differential digital inputs, wherein the set of differential digital inputs are utilized for controlling at least one tri-state current Digital-to-Analog Converter (DAC) cell of a tri-state current DAC, and the tri-state current DAC cell has a positive output current state, a zero output current state and a negative output current state; and when the logical states of the set of differential digital inputs instruct the tri-state current DAC cell should output no positive/negative current, controlling the tri-state current DAC cell to switch to the zero output current state, temporarily decreasing a direct current passing through a middle path of the tri-state current DAC cell. An associated tri-state current DAC is also provided, where the tri-state current DAC includes: the at least one tri-state current DAC cell; and a control device.

Abstract: A delta-sigma analog-to-digital conversion apparatus for receiving an analog input signal to generate a digital output signal includes a subtracting unit, a quantizer, and a feedback unit. The subtracting unit is utilized for performing a subtraction function to generate a subtracted signal according to the analog input signal and a feedback signal. The quantizer is coupled to the subtracting unit and utilized for performing quantization to generate a quantized signal according to the subtracted signal. The feedback unit is coupled between the subtracting unit and the quantizer, and utilized for providing the feedback signal to the subtracting unit according to the quantized signal. The subtracting unit is arranged to reduce signal input swing of the quantizer.

Abstract: A data weighted average circuit is disclosed which includes a lookup unit and a storage unit. The invention uses a lookup table to speed up the circuit operation. Besides, the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data.

Abstract: The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention.

Abstract: The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, extra frequency compensating components for compensating the transistor of the output stage circuit is no longer necessary, and saving circuit layout area and cost can be achieved by the present invention.

Abstract: A filter applied in a sigma-delta modulator includes an integrator, a signal attenuator and a feedback circuit, in which these components are connected in series sequentially to form a local feedback circuit. The integrator integrates an input signal to output an integral signal. Accordingly, the signal attenuator attenuates the integral signal to output an attenuation signal to the local feedback circuit so as to share a part of attenuation amount to reduce the chip area of the sigma-delta modulator.

Abstract: The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention.

Abstract: The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, extra frequency compensating components for compensating the transistor of the output stage circuit is no longer necessary, and saving circuit layout area and cost can be achieved by the present invention.

Abstract: A data weighted average circuit is disclosed which includes a lookup unit and a storage unit. The invention uses a lookup table to speed up the circuit operation. Besides, the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data.

Abstract: An amplifier includes: an input stage for receiving an input signal to generate a first signal corresponding to a first band; a first modulator coupled to the input stage for modulating the first signal to generate a second signal corresponding to a second band; an amplifier stage coupled to the first modulator for processing the second signal to generate a third signal, wherein the third signal includes a fourth signal corresponding to the second band and a first interference signal corresponding to the first band; and a second modulator coupled to the amplifier stage for modulating the third signal to generate a fifth signal corresponding to the first band and to generate a second interference signal corresponding to the second band.

Abstract: A sigma-delta modulator includes a first adder, a filter, a quantizer and a digital-to-analog converter. The first adder receives an input signal and an analog signal and subtracts the analog signal from the input signal to output a processed signal. The filter receives the processed signal to output a filtered signal. The quantizer receives the filtered signal to generate an output signal. The quantizer works based on a first positive reference voltage and a first negative reference voltage. The digital-to-analog converter generates the analog signal according to the output signal and outputs the analog signal to the first adder. The digital-to-analog converter works based on a second positive reference voltage and a second negative reference voltage. A difference between the first positive reference voltage and the first negative reference voltage is smaller than a difference between the second positive reference voltage and the second negative reference voltage.

Abstract: A reference voltage generating circuit includes a first capacitor having a first end and a second end; a second capacitor having a third end and a fourth end; a first switch for selectively coupling a predetermined voltage to the first end of the first capacitor; a second switch for selectively coupling the third end of the second capacitor to the first end of the first capacitor; a third switch for selectively coupling the first end of the first capacitor to a reference voltage level; and a fourth switch for selectively coupling the second end of the first capacitor to a reference voltage level; wherein the first capacitor samples the predetermined voltage in a first stage and re-distributes charges to the second capacitor in a second stage.

Abstract: A filter applied in a sigma-delta modulator includes an integrator, a signal attenuator and a feedback circuit, in which these components are connected in series sequentially to form a local feedback circuit. The integrator integrates an input signal to output an integral signal. Accordingly, the signal attenuator attenuates the integral signal to output an attenuation signal to the local feedback circuit so as to share a part of attenuation amount to reduce the chip area of the sigma-delta modulator.

Abstract: An analog front end circuit is provided, which comprises at least one converting circuit. Each converting circuit further comprises a clamper, a low-pass filter, an input buffer and a sigma-delta analog-to-digital converter. By using the sigma-delta analog to digital converter, the invention not only increases the resolution, but reduces the order of an anti-aliasing filter, therefore reducing the size and the power consumption of the analog circuit.

Abstract: A sigma-delta modulator includes a first adder, a filter, a quantizer and a digital-to-analog converter. The first adder receives an input signal and an analog signal and subtracts the analog signal from the input signal to output a processed signal. The filter receives the processed signal to output a filtered signal. The quantizer receives the filtered signal to generate an output signal. The quantizer works based on a first positive reference voltage and a first negative reference voltage. The digital-to-analog converter generates the analog signal according to the output signal and outputs the analog signal to the first adder. The digital-to-analog converter works based on a second positive reference voltage and a second negative reference voltage. A difference between the first positive reference voltage and the first negative reference voltage is smaller than a difference between the second positive reference voltage and the second negative reference voltage.