Abstract: A liquid crystal display (LCD) device includes a display including a plurality of pixels, a voltage compensation controller configured to control the plurality of pixels and determine whether to compensate a predetermined grayscale voltage to be applied to the plurality of pixels, and a voltage generator configured to provide the predetermined grayscale voltage to the plurality of pixels in response to the voltage compensation controller determining not to compensate the predetermined grayscale voltage, and to compensate the predetermined grayscale voltage and provide the compensated predetermined grayscale voltage to the plurality of pixels in response to the voltage compensation controller determining to compensate the predetermined grayscale voltage.

Abstract: A liquid crystal display (LCD) device includes a display including a plurality of pixels, a voltage compensation controller configured to control the plurality of pixels and determine whether to compensate a predetermined grayscale voltage to be applied to the plurality of pixels, and a voltage generator configured to provide the predetermined grayscale voltage to the plurality of pixels in response to the voltage compensation controller determining not to compensate the predetermined grayscale voltage, and to compensate the predetermined grayscale voltage and provide the compensated predetermined grayscale voltage to the plurality of pixels in response to the voltage compensation controller determining to compensate the predetermined grayscale voltage.

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads include first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract: A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge.

Abstract: A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip.

Abstract: A data driver driving a display panel includes a data processing unit receiving digital data synchronously with a master clock signal and storing the digital signal, and a driving signal output unit generating a driving signal corresponding to the digital data in response to a driving instruction signal, and outputting the driving signal to the display panel. The data processing unit is activated at an activation time determined according to a setting signal.

Abstract: A semiconductor chip for a tape automated bonding (TAB) package is disclosed. The semiconductor chip comprises a connection surface including a set of input pads connected to internal circuitry of the chip and for conveying external signals to the internal circuitry, the set of input pads comprising all of the input pads on the chip. The connection surface includes a set of output pads connected to internal circuitry of the chip and for conveying internal chip signals to outside the chip, the set of output pads comprising all of the output pads on the chip. The connection surface includes a first edge and a second edge that are substantially parallel to each other and are opposite each other on a respective first side and second side of the chip, and a third edge and fourth edge that are substantially perpendicular to the first and second edges, and are opposite each other on a respective third side and fourth side of the chip.

Abstract: Panel source driver circuits include a first data register and a second data register. A common data demultiplexer coupled to the first and second data registers is configured to provide control data from a first input of the demultiplexer to the first data register and control data from a second input of the demultiplexer to the second data register in a first operation mode and to provide control data from the second input to the first data register and control data from the first input to the second register in a second operation mode responsive to an operation mode select signal. A first decoder is coupled to an output of the first data register that is configured to select one of a plurality of first voltages having different levels responsive to the output of the first data register and to output the selected first voltage.

Abstract: Panel source driver circuits include a first data register and a second data register. A common data demultiplexer coupled to the first and second data registers is configured to provide control data from a first input of the demultiplexer to the first data register and control data from a second input of the demultiplexer to the second data register in a first operation mode and to provide control data from the second input to the first data register and control data from the first input to the second register in a second operation mode responsive to an operation mode select signal. A first decoder is coupled to an output of the first data register that is configured to select one of a plurality of first voltages having different levels responsive to the output of the first data register and to output the selected first voltage.

Abstract: The invention, in part, provides a method of (and corresponding apparatus for) receiving (and similarly transmitting) data signals over data lines. Such a method of receiving comprises: organizing said data lines into groups, each group having N input data signals and M reference signals, wherein N is a non-zero, positive integer; associating M reference signals on M reference lines with each group of N input data lines, wherein M is a non-zero, positive integer and N>M; and receiving data on said data lines and reference signals on said reference lines; and determining, for each group, data values on said data lines according to differences between signal parameters on said N data lines and signal parameters on said M reference lines, respectively.

Abstract: There is provided a source driver having a repair amplifier and method of processing signals. There is also provided a liquid crystal display device containing the source driver. The source driver drives adjacent source lines with source line driving signals. The repair amplifier amplifies the source line driving signal to drive a part of a source line.

Abstract: Example embodiments relate to an output buffer having a differential input circuit configured to convert a differential voltage signal input through a positive input terminal and a negative input terminal into a differential current signal, and configured to output the differential current signal. The differential input circuit may include a plurality of PMOS transistors and a plurality of NMOS transistors. The output buffer may further include a slew rate matching circuit configured to compensate for a difference between components of a first parasitic capacitor formed around the plurality of PMOS transistors and components of a second parasitic capacitor formed around the plurality of NMOS transistors.

Abstract: A data line driver includes a circuit that is configured to drive data lines of a display panel in response to digital image data, a horizontal start signal and a load signal. The circuit is further configured to internally generate a frame recognition signal from the horizontal start signal and the load signal. The circuit may also be configured to receive the digital input data, the horizontal start signal and the load signal from a timing controller. The data line driver circuit may be combined with the timing controller, a scan line driver and a display panel to provide a display device. Analogous display data line driving methods also may be provided.

Abstract: Panel source driver circuits include a first data register and a second data register. A common data demultiplexer coupled to the first and second data registers is configured to provide control data from a first input of the demultiplexer to the first data register and control data from a second input of the demultiplexer to the second data register in a first operation mode and to provide control data from the second input to the first data register and control data from the first input to the second register in a second operation mode responsive to an operation mode select signal. A first decoder is coupled to an output of the first data register that is configured to select one of a plurality of first voltages having different levels responsive to the output of the first data register and to output the selected first voltage.

Abstract: An integrated circuit device includes a liquid crystal display (LCD) driver circuit. This LCD driver circuit includes a decoder and a multi-stage sample-hold circuit coupled to an output of the decoder. The LCD driver circuit supports different contrasts for the red, blue and green color signals. In particular, the LCD driver circuit is configured to convert red, blue and green data input signals having equivalent digital values into red, blue and green data output signals having unequal analog values (corresponding to different contrast levels).

Abstract: There is provided a source driver having a repair amplifier and method of processing signals. There is also provided a liquid crystal display device containing the source driver. The source driver drives adjacent source lines with source line driving signals. The repair amplifier amplifies the source line driving signal to drive a part of a source line.

Abstract: The invention, in part, provides a method of (and corresponding apparatus for) receiving (and similarly transmitting) data signals over data lines. Such a method of receiving comprises: organizing said data lines into groups, each group having N input data signals and M reference signals, wherein N is a non-zero, positive integer; associating M reference signals on M reference lines with each group of N input data lines, wherein M is a non-zero, positive integer and N>M; and receiving data on said data lines and reference signals on said reference lines; and determining, for each group, data values on said data lines according to differences between signal parameters on said N data lines and signal parameters on said M reference lines, respectively.

Abstract: A thin film transistor (TFT) liquid crystal device (LCD) driver capable of reducing current consumption is provided. The TFT LCD driver includes a gate driver for driving gate lines of a panel formed of a plurality of transistors and capacitors, and a source driver for driving source lines of the panel. The source driver includes a shift register portion, a latch clock signal generating portion, and a data latching portion. The shift register portion includes first through n-th flip-flops, into which a multiplied signal of an external clock signal is input as a clock signal, and input and output terminals of the flip-flops are connected in series, and provides a driving pulse signal as an input signal of the first flip-flop in response to the clock signal.

Abstract: A decoder for reducing a test time for detecting defective switches in a digital-to-analog converter includes a switch controlling portion for receiving a plurality of digital input signals having information about analog output signals and at least one test order signal for ordering a normal mode or a test mode, outputting the plurality of digital input signals and inverted signals of the plurality of digital input signals when the test order signal orders the normal mode, and outputting as control signals the plurality of digital input signals and second signals having the same phase as the plurality of digital input signals when the test order signal orders the test mode; a plurality of groups of switches each connected in series to a direct current voltage source; and a switch portion for switching the plurality of direct current voltage sources as a function of the plurality of control signals of the switch controlling portion.

Abstract: A thin film transistor (TFT) liquid crystal device (LCD) driver capable of reducing current consumption is provided. The TFT LCD driver includes a gate driver for driving gate lines of a panel formed of a plurality of transistors and capacitors, and a source driver for driving source lines of the panel. The source driver includes a shift register portion, a latch clock signal generating portion, and a data latching portion. The shift register portion includes first through n-th flip-flops, into which a multiplied signal of an external clock signal is input as a clock signal, and input and output terminals of the flip-flops are connected in series, and provides a driving pulse signal as an input signal of the first flip-flop in response to the clock signal.