Abstract: Discussed is a display device and a method of manufacturing the same, wherein the display comprises an upper substrate; a lower substrate provided under the upper substrate, wherein the lower substrate extends to be longer than the upper substrate so as to expose a pad region provided at one side of the lower substrate; a panel driver on the pad region of the lower substrate; an exposure prevention member formed on the panel driver, for preventing the panel driver from being exposed to the external; and an upper film formed on the exposure prevention member.

Abstract: Provided is a method for modeling an ESD breakdown current. According to one variation, a first proportional constant is based on a circumference of the ESD protection device and a second proportional constant based on an area of the ESD protection device. A dual first order equation is derived by sampling circumferences and areas of two ESD protection devices. According to another variation, an equation is defined in which a third value (an ESD breakdown current) is a sum of a first value and a second value, the first value being obtained by multiplying a circumference of an ESD protection device by a first proportional constant, the second value being obtained by multiplying an area of the ESD protection device by a second proportional constant. Then, circumferences and areas of first and second ESD protection samples are calculated. Next, first and second equations are derived by reflecting the first and second circumferences and areas to the equation.

Abstract: A semiconductor device and a method for measuring an analog channel resistance thereof are provided. The semiconductor device includes a substrate, a gate insulating layer and a gate formed on the substrate, a source and a drain formed in the substrate and at both sides of the gate, a source sense connected to the source, and a drain sense connected to the drain.

Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.

Abstract: There are provided a printed circuit board having a structure for relieving a stress concentration on an outer most lead of leads, due to a difference in thermal expansion coefficients between the semiconductor device and the printed circuit board when the semiconductor device is mounted on the printed circuit board. The printed circuit board includes an inner lead portion to be connected to the semiconductor device. The inner lead portion includes a plurality of leads, arranged in parallel with a same pitch in a predetermined area, and additional leads located near both ends of the predetermined area in which the plurality of leads are arranged in parallel, respectively, wherein each of the plurality of leads has a pitch smaller than 30 ?m and a width of the additional lead is wider than 20 ?m. There are also provided a semiconductor chip package equipped with the printed circuit board according to the present invention.

Abstract: A semiconductor device and a method for measuring an analog channel resistance thereof are provided. The semiconductor device includes a substrate, a gate insulating layer and a gate formed on the substrate, a source and a drain formed in the substrate and at both sides of the gate, a source sense connected to the source, and a drain sense connected to the drain.

Abstract: A semiconductor device and a method for measuring an analog channel resistance thereof are provided. The semiconductor device includes a substrate, a gate insulating layer and a gate formed on the substrate, a source and a drain formed in the substrate and at both sides of the gate, a source sense connected to the source, and a drain sense connected to the drain.

Abstract: Provided is a method for modeling an ESD breakdown current. According to one variation, a first proportional constant is based on a circumference of the ESD protection device and a second proportional constant based on an area of the ESD protection device. A dual first order equation is derived by sampling circumferences and areas of two ESD protection devices. According to another variation, an equation is defined in which a third value (an ESD breakdown current) is a sum of a first value and a second value, the first value being obtained by multiplying a circumference of an ESD protection device by a first proportional constant, the second value being obtained by multiplying an area of the ESD protection device by a second proportional constant. Then, circumferences and areas of first and second ESD protection samples are calculated. Next, first and second equations are derived by reflecting the first and second circumferences and areas to the equation.

Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.

Abstract: Disclosed is a system and method for automatically measuring carrier density distribution by using capacitance-voltage characteristics of a MOS transistor device. System comprises an automatic probe station for measurement of an object wafer, the automatic probe station being electrically connected to the wafer; a capacitor measuring unit having a high frequency terminal and a low frequency terminal; and a control computer for being respectively connected the automatic probe station and the capacitor measuring unit, wherein the high frequency terminal is connected to a gate of the wafer and the low frequency terminal is connected to a substrate of the wafer.

Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.

Abstract: A semiconductor device and a method for measuring an analog channel resistance thereof are provided. The semiconductor device-includes-a substrate, a gate insulating layer and a gate formed on the substrate, a source and a drain formed in the substrate and at both sides of the gate, a source sense connected to the source, and a drain sense connected to the drain.

Abstract: A method of measuring flat-band status capacitance of a gate oxide in a MOS transistor device is disclosed. According to the method of measuring flat-band status capacitance of gate oxide in MOS transistor device, flat-band status capacitance of gate oxide in MOS transistor device can be automatically measured and immediately analyzed by using a characteristics measuring system that changes in accordance with a gate voltage.

Abstract: A method for detecting an abnormal condition of a MOS transistor in a subthreshold region. The method includes measuring a variation in a drain current with respect to a variation of a gate voltage of the MOS transistor to obtain a characteristics curve, and calculating, with reference to the obtained characteristics curve, a variation of transconductance with respect to each of the gate voltages to obtain a transconductance variable curve. The transconductance variable curve is differentiated. A number of inflection points in a curve obtained by the differentiation is determined to indicate the abnormal condition of the MOS transistor.

Abstract: Provided is a vehicle tire with an RFID tag. The damage of the RFID tag or non-recognition problem can be prevented when a severe operating atmosphere is applied to the tire. The RFID tag is mounted on a side of the tire, apart from a bead included on an inner circumference of the tire, within a distance of 0.74 in a radial direction from the bead toward a belt attached to an outer circumference of the tire assuming that the distance from the bead to the belt is 1.

Abstract: A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient ?upper of the upper part is defined by the Equation of ? upper = ? i = 1 n ? ? i × E i × v i ? i = 1 n ? E i × v i , where ?i is respective thermal expansion coefficients of, Ei is respective elastic moduli of, and vi is respective volume ratios of first through nth components constituting the upper part (e.g.

Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.

Abstract: Provided is a vehicle tire with an RFID tag. The damage of the RFID tag or non-recognition problem can be prevented when a severe operating atmosphere is applied to the tire. The RFID tag is mounted on a side of the tire, apart from a bead included on an inner circumference of the tire, within a distance of 0.74 in a radial direction from the bead toward a belt attached to an outer circumference of the tire assuming that the distance from the bead to the belt is 1.

Abstract: A parent or master substrate for a semiconductor package is provided, which can provide a plurality of unit substrates by cutting into pieces for producing a semiconductor device. The parent substrate includes an insulation layer, conductor patterns formed on first and second surfaces of the insulation layer, and PSR (photo solder resist) layers respectively formed on the first and second surfaces of the insulation layers and covering the conductor patterns. The parent substrate includes an upper part and a lower part divided by a reference surface which passes through the center of the insulation layer. When an equivalent thermal expansion coefficient ?upper of the upper part is defined by the Equation of ? upper = ? i = 1 n ? ? i × E i × v i ? i = 1 n ? E i × v i , where ?i is respective thermal expansion coefficients of, Ei is respective elastic moduli of, and vi is respective volume ratios of first through nth components constituting the upper part (e.g.

Abstract: There are provided a printed circuit board having a structure for relieving a stress concentration on an outer most lead of leads, due to a difference in thermal expansion coefficients between the semiconductor device and the printed circuit board when the semiconductor device is mounted on the printed circuit board. The printed circuit board includes an inner lead portion to be connected to the semiconductor device. The inner lead portion includes a plurality of leads, arranged in parallel with a same pitch in a predetermined area, and additional leads located near both ends of the predetermined area in which the plurality of leads are arranged in parallel, respectively, wherein each of the plurality of leads has a pitch smaller than 30 ?m and a width of the additional lead is wider than 20 ?m. There are also provided a semiconductor chip package equipped with the printed circuit board according to the present invention.