Patents by Inventor Chang SU
Chang SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971844Abstract: A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.Type: GrantFiled: November 29, 2022Date of Patent: April 30, 2024Assignee: SUNPLUS TECHNOLOGY CO., LTD.Inventors: Hsing-Sheng Huang, Hao-Chang Chang, Ming-Chang Su, Hwan-Rei Lee
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Publication number: 20240133417Abstract: Provided is an L-shaped bolt fastening structure using a hole guard, which is capable of being installed in holes having various sizes. Since an L-shaped bolt is fastened in a state in which a hole guard is mounted on a lower structure, fastening using the L-shaped bolt is applicable to a steel pad having a large hole or a large long hole or a grating in which holes are damaged and have irregular sizes. Since bolts can be installed in holes having various sizes in one direction using the hole guard and the L-shaped bolt, the L-shaped bolt fastening structure using the hole guard has a wide range of applications in a floor in an industrial site and as a hook hanger or the like of an H-beam structure, a ceiling, or a wall structure of a construction site.Type: ApplicationFiled: May 3, 2023Publication date: April 25, 2024Inventor: Chang Su LIM
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Publication number: 20240133416Abstract: Disclosed is an L-shaped bolt fastening structure for upright fastening which is capable of quickly and firmly fixing equipment to a support structure such as a grating plate without changing the installed grating plate. Since a bent portion of an L-shaped bolt includes a locking groove and an upright auxiliary portion, in a state in which the L-shaped bolt is upright, a fixing nut can be fastened. Accordingly, the fixing nut can be easily and quickly coupled, and also a correct coupling posture can be implemented even after the fixing nut is completely tightened. In addition, since a coupling long hole washer that is divided and coupled is added between a bracket and a fixing nut, when the fixing nut is fastened to the L-shaped bolt, the fixing nut can be fastened in a state in which the L-shaped bolt is upright.Type: ApplicationFiled: March 22, 2023Publication date: April 25, 2024Inventor: Chang Su LIM
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Publication number: 20240125737Abstract: An internal detection system of stress concentration of an oil and gas pipeline based on unsaturated orthogonally magnetization is provided. The system comprises a detection device and a processing device; the detection device comprises a detection probe; the detection probe comprises a magnetizing device and a magnetic signal acquisition device; the magnetizing device is fixedly connected with the magnetic signal acquisition device; the magnetizing device is configured to magnetize a pipeline to be detected, so that the pipeline generates a magnetized magnetic field; the magnetic signal acquisition device is configured to acquire a magnetic signal of the magnetized magnetic field to obtain an acquired signal and send the acquired signal to the processing device; the processing device is configured to receive the acquired signal and obtain a stress concentration area of the pipeline based on the acquired signal.Type: ApplicationFiled: October 12, 2023Publication date: April 18, 2024Applicant: China Special Equipment Inspection & Research InstituteInventors: Jinzhong CHEN, Jiaxing XIN, Runkun LU, Chang LIU, Zhengda SU, Qingbao ZHANG, Guannan SHI, Yanbao GUO
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Patent number: 11962247Abstract: A resonant half-bridge flyback power converter includes: a first transistor and a second transistor which form a half-bridge circuit; a transformer and a resonant capacitor connected in series and coupled to the half-bridge circuit; and a switching control circuit configured to generate a first driving signal and a second driving signal to control the first transistor and the second transistor respectively for switching the transformer to generate an output voltage. The first driving signal is configured to magnetize the transformer. The second driving signal includes at most one pulse between two consecutive pulses of the first driving signal. The switching control circuit generates a skipping cycle period when an output power is lower than a predetermined threshold. A resonant pulse of the second driving signal is skipped during the skipping cycle period. The skipping cycle period is increased in response to the decrease of the output power.Type: GrantFiled: February 16, 2022Date of Patent: April 16, 2024Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Ta-Yung Yang, Ying-Chieh Su, Yu-Chang Chen
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Patent number: 11963386Abstract: A display apparatus includes a base substrate, a light emitting structure disposed on the base substrate, and a thin film encapsulation layer disposed on the light emitting structure and including at least one inorganic layer and at least one organic layer. The at least one inorganic layer includes a high density layer having a density of greater than or equal to about 2.0 g/cm3 and a low density layer having a density of less than about 2.0 g/cm3. The high density layer and the low density layer are in contact with each other.Type: GrantFiled: September 2, 2022Date of Patent: April 16, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Chang Yeong Song, Won Jong Kim, Yi Su Kim, Jong Woo Kim, Hye In Yang, Woo Suk Jung, Yong Chan Ju, Jae Heung Ha
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Publication number: 20240120276Abstract: A three-dimensional semiconductor integrated circuit device including an inter-die interface is provided. The device includes a top die including a plurality of micro cells provided on a top surface of the top die, a plurality of micro bumps provided on a bottom surface of the top die, and wiring patterns connecting the plurality of micro cells to the plurality of micro bumps; and a bottom die including a plurality of macro cells provided on a top surface thereof, wherein the plurality of macro cells are electrically connected to the plurality of micro bumps, respectively, wherein a size of a region in which the plurality of micro cells are provided is smaller than a size of a region in which the plurality of micro bumps are provided.Type: ApplicationFiled: July 27, 2023Publication date: April 11, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Seung CHOI, Byung-Su KIM, Bong Il PARK, Chang Seok KWAK, Sun Hee PARK, Sang Joon CHEON
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Patent number: 11955705Abstract: A multi-input multi-output antenna system capable of being disposed in an electronic device and the electronic device including the antenna system have a low-frequency antenna assembly and a high-frequency antenna assembly. The low-frequency antenna assembly includes multiple low-frequency antennas that are spaced apart from each other by a distance. The high-frequency antenna assembly includes multiple high-frequency antennas that are spaced apart from each other by a distance. One of the high-frequency antennas is structured as a low-profile dish antenna and is located between the low-frequency antennas, so that the antenna system has smaller volume and height, and better isolation and radiation patterns.Type: GrantFiled: June 13, 2022Date of Patent: April 9, 2024Assignee: Alpha Networks Inc.Inventors: De-Chang Su, Chih Jen Cheng
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Publication number: 20240112959Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
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Publication number: 20240111935Abstract: A method of generating an IC layout diagram includes receiving the IC layout diagram including an active region, a gate region extending across the active region from a first active region edge to a second active region edge, and a gate via positioned at a location along the gate region between the first and second edges, configuring a delta resistance network including the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges, and performing a simulation based on the delta resistance network.Type: ApplicationFiled: November 27, 2023Publication date: April 4, 2024Inventors: Ke-Ying SU, Ke-Wei SU, Keng-Hua KUO, Lester CHANG
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Patent number: 11945461Abstract: Disclosed are a drunk driving prevention system and a method of controlling the system that includes a sensor module measuring a alcohol content in the exhaled breath of a driver during a breath-checking of the driver and a control module configured to check the intoxication state of the driver from the alcohol content measured by the sensor module to determine whether the breath-checking is complete and block an engine start when the breath-checking fails, wherein the control module includes a check unit displaying breath-checking guide information through a display unit and the check unit displays the breath-checking guide information based on an engine start input of the driver.Type: GrantFiled: July 29, 2022Date of Patent: April 2, 2024Assignee: HYUNDAI MOBIS CO., LTD.Inventors: Yu Jin Jung, Yeon Su Kim, June Seung Lee, Chang Won Lee
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Publication number: 20240105719Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Kuo-Cheng Ching, Huan-Chieh Su, Zhi-Chang Lin, Chih-Hao Wang
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Patent number: 11942550Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.Type: GrantFiled: February 24, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Chih Teng Hsu, Chih-Chiang Chang, Chien-I Kuo, Chii-Horng Li, Yee-Chia Yeo
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Publication number: 20240094251Abstract: A test socket including: a testing probe including a lower plunger in contact with a pad; an upper plunger coupled to the lower plunger; a spring probe made of a cylindrical spring for applying elasticity to the lower plunger and the upper plunger; and a contact probe with an upper side contacting a terminal of a test device and a lower side contacting the upper plunger; a socket housing that provides housing holes and accommodates the contact probe and the spring probe so that an upper side of the contact probe protrudes at each housing hole; and a cover that provides cover holes and is fastened to the socket housing so that a lower side of the lower plunger protrudes at each cover hole, wherein the upper plunger provides a sliding groove, the lower plunger provides a pair of sliding protrusions inserted into the sliding groove.Type: ApplicationFiled: September 18, 2023Publication date: March 21, 2024Applicant: TSE CO., LTDInventor: Chang Su OH
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Patent number: 11935794Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.Type: GrantFiled: December 12, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu
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Patent number: 11935981Abstract: A photo-detecting device includes a first semiconductor layer with a first dopant, a light-absorbing layer, a second semiconductor layer, and a semiconductor contact layer. The second semiconductor layer is located on the first semiconductor layer and has a first region and a second region, the light absorbing layer is located between the first semiconductor layer and the second semiconductor layer and has a third region and a fourth region, the semiconductor contact layer contacts the first region. The first region includes a second dopant and a third dopant, the second region includes second dopant, and the third region includes third dopant. The semiconductor contact layer has a first thickness greater than 50 ? and smaller than 1000 ?.Type: GrantFiled: June 30, 2021Date of Patent: March 19, 2024Assignee: EPISTAR CORPORATIONInventors: Chu-Jih Su, Chia-Hsiang Chou, Wei-Chih Peng, Wen-Luh Liao, Chao-Shun Huang, Hsuan-Le Lin, Shih-Chang Lee, Mei Chun Liu, Chen Ou
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Patent number: 11931861Abstract: A grinding wheel includes a plurality of wheel tips. The plurality of wheel tips include a plurality of diamond abrasive grains and a bonding material mixed with the diamond abrasive grains. The plurality of diamond abrasive grains have a ratio of a length in a long axis direction to a width in a short axis direction of 1:2.5 to 1:3.5 and includes edges or vertices having a grinding angle of 90° or less.Type: GrantFiled: May 21, 2019Date of Patent: March 19, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong Gi Jeon, Sang Il Choi, Chang Su Jeong, Tae Gyu Kang
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Patent number: 11935969Abstract: A photodetector includes a first semiconductor layer, an absorption structure, a second semiconductor layer, and a barrier structure. The absorption structure is located on the first semiconductor layer, and having a first conduction band, a first valence band, and a first band gap. The second semiconductor layer is located on the absorption structure, and having a second conduction band, a second valence band, and a second band gap. The barrier structure is located between the absorption structure and the second semiconductor layer, and having a third conduction band, a third valence band, and a third band gap. The third conduction band is greater than the second conduction band or the third valence band is less than the second valence band.Type: GrantFiled: November 9, 2020Date of Patent: March 19, 2024Assignee: EPISTAR CORPORATIONInventors: Shih-Chang Lee, Shiuan-Leh Lin, I-Hung Chen, Chu-Jih Su, Chao-Shun Huang
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Patent number: 11929389Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.Type: GrantFiled: May 19, 2021Date of Patent: March 12, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
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Publication number: 20240079524Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.Type: ApplicationFiled: September 6, 2023Publication date: March 7, 2024Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN