Patents by Inventor Chang-Sub Song

Chang-Sub Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8780532
    Abstract: There is provided a solid electrolytic capacitor, including: a condenser element including a chip body molded by sintering, a positive electrode terminal contact layer formed on one area of the chip body to be exposed to the outside, an insulating layer formed in the entire area or some area other than one area in which the positive electrode terminal contact layer is formed, and a negative electrode layer stacked on the insulating layer; a negative electrode extracting layer stacked to be electrically connected with the negative electrode layer; a negative electrode terminal stacked on the negative electrode extracting layer; a positive electrode terminal stacked on the positive electrode terminal contact layer.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: July 15, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Kwang Kim, Jun Suk Jung, Chang Sub Song
  • Publication number: 20120182668
    Abstract: A solid electrolytic capacitor and manufacturing method, in which an oxidation-resistant coating layer configured to surround the surface of a terminal reinforcing material underlies a capacitor element. The solid electrolytic capacitor includes a capacitor element having a positive polarity internally and having one end to which an anode wire is inserted; a cathode leading-out layer; a pair of terminal reinforcing materials coupled with both bottom sides of the capacitor element; an oxidation resistant coating layer surrounding the surface of the pair of terminal reinforcing materials; a mold part surrounding the outer periphery of the capacitor element, while exposing the other end of the anode wire, the other side of the cathode leading-out layer, and the lower surfaces of the pair of terminal reinforcing materials; and anode and cathode terminals formed on both sides of the mold part and the lower surfaces of the terminal reinforcing materials.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 19, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Kwang KIM, Jun Suk Jung, Chang Sub Song
  • Publication number: 20120120554
    Abstract: There is provided a solid electrolytic capacitor, including: a condenser element including a chip body molded by sintering, a positive electrode terminal contact layer formed on one area of the chip body to be exposed to the outside, an insulating layer formed in the entire area or some area other than one area in which the positive electrode terminal contact layer is formed, and a negative electrode layer stacked on the insulating layer; a negative electrode extracting layer stacked to be electrically connected with the negative electrode layer; a negative electrode terminal stacked on the negative electrode extracting layer; a positive electrode terminal stacked on the positive electrode terminal contact layer.
    Type: Application
    Filed: February 24, 2011
    Publication date: May 17, 2012
    Inventors: Jae Kwang Kim, Jun Suk Jung, Chang Sub Song
  • Publication number: 20110127689
    Abstract: An apparatus for manufacturing an electronic component includes: upper and lower metal molds, at least one of which being formed as a porous member on which an electronic component is mounted, including an internal space for accommodating the electronic component therein; a release film providing unit providing a release film to the internal space of the upper and lower metal molds; and a molding resin providing unit providing a molding resin to the internal space to allow the electronic component to be injection-molded.
    Type: Application
    Filed: April 27, 2010
    Publication date: June 2, 2011
    Inventors: Jae Kwang KIM, Chang Sub Song, Jun Suk Jung
  • Patent number: 6229179
    Abstract: A semiconductor device, more particularly, an intelligent power integrated circuit formed on a substrate where a power device and a control device are formed is provided. The intelligent power integrated circuit includes a handling substrate for a first conductivity type, a substrate for a power device of a second conductivity type where a first buffer layer of a concentration higher than that of the substrate for the power device is formed around a surface contacting with the handling substrate, a substrate for a control device formed on an insulating layer partially formed on the substrate for the power device, a control device formed on the substrate for the control device, and a power device vertically formed through the substrate for the power device and the handling substrate.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: May 8, 2001
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Chang-Sub Song, Hyeong-Woo Jang, Sin-Kook Jang