Patents by Inventor Chang Sup Lee
Chang Sup Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105604Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Patent number: 11919688Abstract: According to an embodiment of the present disclosure, a content container is provided. The content container may include: a container part configured to accommodate a liquid content; an upper cap that is detachably coupled to the container part and includes a first accommodation part configured to accommodate a solid content and a pressing part moved by being pressed; and a lower cap that is inserted into the container part, and includes an accommodation tube forming a second accommodation part and a plurality of communication holes formed in the outside of the accommodation tube to communicate with the container part, wherein, by pressing the upper cap, the solid content is moved from the first accommodation part to the second accommodation part.Type: GrantFiled: March 18, 2021Date of Patent: March 5, 2024Assignee: KOLMAR BNH CO., LTDInventors: Chang Soo Lee, Koo Sup Ahn, Jong Hyun Park, Sang In Han, Hye Jin Jung
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Patent number: 11918632Abstract: The present invention provides a method for preventing or treating liver cancer in a subject comprising administrating at least one selected from the group consisting of an Ssu72 peptide, a polynucleotide encoding the Ssu72 peptide and an expression vector containing the polynucleotide to the subject.Type: GrantFiled: July 25, 2022Date of Patent: March 5, 2024Assignees: CUROGEN TECHNOLOGY CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: Chang Woo Lee, Jin Kwan Lee, Hyun Soo Kim, Jae-kyung Kim, Joon Sup Yoon
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Patent number: 11910614Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: GrantFiled: April 1, 2022Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
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Patent number: 11854975Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: GrantFiled: August 27, 2021Date of Patent: December 26, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Publication number: 20230170302Abstract: Disclosed are semiconductor devices and electronic systems including the same. A semiconductor device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes and dielectric layers that are stacked in alternating fashion, each of the plurality of electrodes including an electrode part on the cell array region and a pad part on the connection region, dummy vertical structures on the connection region and penetrating the pad parts of each of the electrodes, and a cell contact plug on the connection region and coupled to the pad part of each of the electrodes. A thickness of the pad part is greater than that of the electrode part. The pad part has a lower portion connected to the electrode part and an upper portion on the lower portion. Between adjacent ones of the dummy vertical structures, a width of the upper portion is not less than that of the lower portion.Type: ApplicationFiled: September 23, 2022Publication date: June 1, 2023Inventors: Jimo Gu, Jiyoung Kim, Woosung Yang, Sukkang Sung, Chang-Sup Lee
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Publication number: 20220328520Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.Type: ApplicationFiled: June 28, 2022Publication date: October 13, 2022Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
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Publication number: 20220223616Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
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Patent number: 11374019Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.Type: GrantFiled: April 1, 2020Date of Patent: June 28, 2022Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
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Patent number: 11309326Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: GrantFiled: March 27, 2020Date of Patent: April 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Patent number: 11296104Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: GrantFiled: April 10, 2020Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
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Publication number: 20210391260Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Patent number: 11107765Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: GrantFiled: April 21, 2020Date of Patent: August 31, 2021Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Patent number: 10886289Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.Type: GrantFiled: April 5, 2018Date of Patent: January 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Shin-hwan Kang, Young-hwan Son, Dong-seog Eun, Chang-sup Lee, Jae-hoon Jang
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Publication number: 20200251417Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.Type: ApplicationFiled: April 21, 2020Publication date: August 6, 2020Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
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Publication number: 20200243554Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
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Publication number: 20200227438Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.Type: ApplicationFiled: April 1, 2020Publication date: July 16, 2020Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
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Publication number: 20200227430Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Patent number: 10658374Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.Type: GrantFiled: May 20, 2019Date of Patent: May 19, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
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Patent number: RE49923Abstract: A multilayer ceramic capacitor includes: a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with respective dielectric layers interposed therebetween; and first and second external electrodes disposed on an external surface of the ceramic body, wherein the dielectric layer contains a barium titanate-based powder particle having a core-shell structure including a core and a shell around the core, the shell having a structure in which titanium is partially substituted with an element having the same oxidation number as that of the titanium in the barium titanate-based powder particle and having an ionic radius different from that of the titanium in the barium titanate-based powder particle, and the shell covers at least 30% of a surface of the core.Type: GrantFiled: June 22, 2021Date of Patent: April 16, 2024Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Woo Kim, Jong Ho Lee, Min Gi Sin, Hak Kwan Kim, Chin Mo Kim, Chi Hwa Lee, Hong Seok Kim, Woo Sup Kim, Chang Hwa Park