Abstract: The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.

Abstract: The method is described for fabricating an integrated circuit having a combination of a capacitor and metal oxide semiconductor field effect transistor with gate electrodes and source/drain regions. The method features the use of silicon nitride or silicon oxynitride barrier layers. The barrier layer is a key to the successful lightly doped drain spacer etch process. The barrier layer aids in endpoint detection for the plasma etch. This allows for less loss of the field oxide and greater thickness control of the field oxide regions. Further, the silicon nitride endpoint detection allows for the removal of undesirable residual silicon oxide from the surface of the capacitor plate without loss of the polysilicon capacitor plate itself.