Abstract: A method for improving an over erasing effect of a charge-trapping memory cell. The charge-trapping memory cell has a transistor, which has a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. First, the method erases the charge-trapping memory cell. Then, after the charge-trapping memory cell is completely erased, the first bit line is electrically connected to the second bit line to make a voltage level of the first bit line equal a voltage level of the second bit line such that the voltage level of the first terminal of the transistor equals the voltage level of the second terminal of the transistor.

Abstract: A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the nth transistor are respectively transformed into a source voltage and a drain voltage in an nth reading period, and the voltage level of the second terminal of the (n+1)th transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mth transistor are respectively transformed into the source voltage and the drain voltage in an mth reading period. The source voltage equals the ground voltage.

Abstract: Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does not allow time for precharging a second word line.

Abstract: Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does not allow time for precharging a second word line.

Abstract: Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does not allow time for precharging a second word line.

Abstract: A memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.

Abstract: Various methods and apparatuses permit high speed reads of memory. Portions of data are copied and stored on other word lines. By reading a copy of data that is stored on memory cells accessed by a word line that is already precharged, a latency specification can be met which does not allow time for precharging a second word line.

Abstract: In one embodiment, a memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.

Abstract: A semiconductor memory with shielding effect is disclosed in the invention. The memory includes at least a plurality of word lines, one ground line control unit, and a plurality of memory units. Every memory unit includes a primary bit line, a ground line, a first equivalent switch, and a second equivalent switch. The primary bit line is enabled by a control signal. The ground line and the ground line control unit are electrically connected. The first equivalent switch is coupled to both the primary bit line and the ground line, and is controlled by the control signal of the previous memory unit. The second equivalent switch is coupled to both the primary bit line and the ground line of the next memory unit, and is controlled by the control signal of the next memory unit.

Abstract: A semiconductor memory with shielding effect is disclosed in the invention. The memory includes at least a plurality of word lines, one ground line control unit, and a plurality of memory units. Every memory unit includes a primary bit line, a ground line, a first equivalent switch, and a second equivalent switch. The primary bit line is enabled by a control signal. The ground line and the ground line control unit are electrically connected. The first equivalent switch is coupled to both the primary bit line and the ground line, and is controlled by the control signal of the previous memory unit. The second equivalent switch is coupled to both the primary bit line and the ground line of the next memory unit, and is controlled by the control signal of the next memory unit.