Patents by Inventor CHANG TZU LIN

CHANG TZU LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10564706
    Abstract: A power source analysis method includes receiving a target number, performing voltage drop analysis on a plurality of power sources in a power delivery network (PDN) to determine respective supply currents of the power sources, sorting the supply currents of the power sources, and selecting a plurality of target power sources from the power sources according to a sorted result. The total number of the selected target power sources equals the target number.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: February 18, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Tzu Lin, Ding-Ming Kwai, I-Hsuan Lee
  • Patent number: 10339253
    Abstract: A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 2, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chi-Han Lee, Ding-Ming Kwai, Chang-Tzu Lin, I-Hsuan Lee
  • Patent number: 10289141
    Abstract: A method for generating a power distribution network (PDN) is provided. A heterogeneous circuit data is input. A plurality of horizontal power lines and a plurality of vertical power lines are determined according to the heterogeneous circuit data. A PDN model of the heterogeneous circuit is determined according to the horizontal power lines and the vertical power lines. Power consumption value is assigned to a plurality of internal nodes of the PDN model of the heterogeneous circuit. The PDN model of the heterogeneous circuit is adjusted to meet a target voltage drop limitation of the heterogeneous circuit data.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 14, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Tzu Lin, Ding-Ming Kwai, Tzu-Min Lin
  • Publication number: 20190121930
    Abstract: A method of yield prejudgment and bump re-assignment for a die is provided. The die includes a plurality of areas. Each area is electrically connected to a substrate through a corresponding bump. The successful-connection probability of each area is prejudged. The die is divided into a signal region and a short-circuit region according to the successful-connection probabilities. The positions of the bumps are arranged so that signal bumps are disposed in the signal region and power bumps are disposed in the short region.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 25, 2019
    Inventors: Chi-Han Lee, Ding-Ming Kwai, Chang-Tzu Lin, I-Hsuan Lee
  • Publication number: 20180157314
    Abstract: A power source analysis method includes receiving a target number, performing voltage drop analysis on a plurality of power sources in a power delivery network (PDN) to determine respective supply currents of the power sources, sorting the supply currents of the power sources, and selecting a plurality of target power sources from the power sources according to a sorted result. The total number of the selected target power sources equals the target number.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 7, 2018
    Inventors: Chang-Tzu Lin, Ding-Ming Kwai, I-Hsuan Lee
  • Publication number: 20170023961
    Abstract: A method for generating a power distribution network (PDN) is provided. A heterogeneous circuit data is input. A plurality of horizontal power lines and a plurality of vertical power lines are determined according to the heterogeneous circuit data. A PDN model of the heterogeneous circuit is determined according to the horizontal power lines and the vertical power lines. Power consumption value is assigned to a plurality of internal nodes of the PDN model of the heterogeneous circuit. The PDN model of the heterogeneous circuit is adjusted to meet a target voltage drop limitation of the heterogeneous circuit data.
    Type: Application
    Filed: November 18, 2015
    Publication date: January 26, 2017
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Tzu LIN, Ding-Ming KWAI, Tzu-Min LIN
  • Patent number: 9183345
    Abstract: An apparatus and method for generating a power delivery network (PDN) of a circuit system is provided. The apparatus performs a power diagnostics on the PDN of a circuit system. According to result of the power diagnostics, a number of areas are generated and divided into at least three subsets. At least one area is selected from each of the at least three subsets, and one node is selected from each of the selected areas, and the nodes are connected sequentially to form an interconnection with at least three nodes in the PDN.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: November 10, 2015
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Tzu Lin, Ding-Ming Kwai, Tsu-Wei Tseng
  • Publication number: 20150199467
    Abstract: An apparatus and method for generating a power delivery network (PDN) of a circuit system is provided. The apparatus performs a power diagnostics on the PDN of a circuit system. According to result of the power diagnostics, a number of areas are generated and divided into at least three subsets. At least one area is selected from each of the at least three subsets, and one node is selected from each of the selected areas, and the nodes are connected orderly to form an interconnection with at least three nodes in the PDN.
    Type: Application
    Filed: July 8, 2014
    Publication date: July 16, 2015
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chang-Tzu LIN, Ding-Ming KWAI, Tsu-Wei TSENG
  • Patent number: 8689160
    Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 1, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Chang Tzu Lin, Ding Ming Kwai
  • Publication number: 20130283224
    Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.
    Type: Application
    Filed: June 17, 2013
    Publication date: October 24, 2013
    Inventors: CHANG TZU LIN, DING MING KWAI
  • Patent number: 8522186
    Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: August 27, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Chang Tzu Lin, Ding Ming Kwai
  • Publication number: 20130159950
    Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: CHANG TZU LIN, DING MING KWAI