Abstract: Methods, memories and systems to access a memory may include generating an address during a first time period, decoding the address during the first time period, and selecting one or more cells of a buffer coupled to a memory array based, at least in part, on the decoded address, during a second time period.

Abstract: Methods, memories and systems to access a memory may include generating an address during a first time period, decoding the address during the first time period, and selecting one or more cells of a buffer coupled to a memory array based, at least in part, on the decoded address, during a second time period.

Abstract: The present invention discloses a circuit for both detecting and confirming the memory cell which can verify the state of program and erasure on the memory cell when it performs a programming and an erasure onto or out of the memory cell after a normal read-out operation.

Abstract: A security read only memory(ROM) device for maintaining security of data therein is provided. The ROM device comprises a security memory cell array 11 including a storage cell array for storing user program data and a security code cell array for storing security code data, and a control section 14 for providing a signal depending on the comparison result from the comparison section 11 so that if the external input data are equal to security code data in all addresses, the data stored in the storage cell array can be read during power-on and if not, regardless of power-on-on/off states, the data stored in the storage cell array can not be read.

Abstract: In accordance of the invention, the Erasable and Programmable Logic Device comprising a test circuit of the input architectures is provided.The test circuit comprises an extra test line 39, a plurality of EPROM transistors 34 having respectively the drain thereof connected to the extra test line and the gate thereof connected to a true input line provided from said one input architecture, sensing means 36 connected to the extra test line for sensing the state of the extra test line, and a buffer circuit 37 connected to the sensing means.

Abstract: A test circuit 2 connected between a programmable "AND" memory array 1 and an Input/Output macrocell 3 in an erasable and programmable logic device, for testing the Input/Output macrocell, comprising, a plurality of bit lines connected to the programmable "AND" memory array and the Input/Output macrocell, a plurality of extra test lines connected to a plurality of exterior pins respectively, a plurality of EPROM(Erasable Programmable Read Only memory) transistors which the drain thereof is connected to the bit line and the gate thereof is connected to the extra test line, wherein the EPROM transistors corresponding to the number of the bit lines connected to one logic sum gate forming a logic sum data path within the Input/Output machrocell are connected to one extra test line, and the other EPROM transistors excepting said EPROM transistors are respectively connected to one bit line and one extra test line.

Abstract: A memory devices having NAND type cells as storage elements is disclosed. The amplifier prevents the error from occurring and improves the sensing speed by getting the column line and the reference line approximately the same current level for a while, after the equalizing signal was just turned into row level, in order that the potentials of the column line and the reference line normally come out without time delay. And, the sensing amplifier comprises a reference cell string selecting part 203 connected to a reference line and to selection lines 1 to N, a reference cell part 204 connected to row lines 1 to N and to the reference cell string selecting part 203, a column dummy cell part 205 connected to a column line and to dummy lines 1 and 2, a reference dummy cell part 206 connected to the reference line and to the dummy lines 1 and 2.

Abstract: In a programmable logic device having a programmable logic array 15 adapted to receive a plurality of input signals and provide a plurality of output signals (product terms) through an AND logic which depend on the input signals and information stored in the logic array and a macrocell associated with the logic array, the macrocell including a first OR gate group 11 including a plurality of OR gates, each for ORing the predetermined number of the product terms from the logic array; a demultiplexor group 12 including a plurality of demultiplexors each coupled to output of the corresponding OR gate in the first OR gate group 11, each for generating two or more output signals per one input signal; a second OR gate group 13 including a plurality of OR gates each coupled to a corresponding one of outputs of each of the plurality of demultiplexors, each for ORing the corresponding outputs from the plurality of demultiplexors to form a sum data path for the product terms; and an input/output circuit 14 for receiving

Abstract: A method for arranging EEPROM cells and a semiconductor device manufactured by the method is disclosed. The semiconductor device with an EEPROM cell arrangement comprises a plurality of segmentized buried diffusion regions formed on a semiconductor substrate with each segmentized buried diffusion region with a diffusion region formed in the semiconductor substrate between a selecting transistor and a buried diffusion region and with a diffusion region formed in the semiconductor substrate between adjacent segmentized buried diffusion regions with a contact formed on each diffusion region to connect the diffusion region to a first conducting layer for resistance reduction. The selecting transistor connects the segmentized buried diffusion regions to a bit line through a first conduction layer for via contact and a second conducting layer for bit line by selecting a predetermined number of segmentized buried diffusion regions.