Patents by Inventor Chang Wen Chen
Chang Wen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021468Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.Type: ApplicationFiled: August 8, 2023Publication date: January 18, 2024Inventors: Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
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Publication number: 20230075664Abstract: Disclosed is a method and system for achieving optimal separable convolutions, the method is applied to image analyzing and processing and comprises steps of: inputting an image to be analyzed and processed; calculating three sets of parameters of a separable convolution: an internal number of groups, a channel size and a kernel size of each separated convolution, and achieving optimal separable convolution process; and performing deep neural network image process. The method and system in the present disclosure adopts implementation of separable convolution which efficiently reduces a computational complexity of deep neural network process. Comparing to the FFT and low rank approximation approaches, the method and system disclosed in the present disclosure is efficient for both small and large kernel sizes and shall not require a pre-trained model to operate on and can be deployed to applications where resources are highly constrained.Type: ApplicationFiled: September 8, 2021Publication date: March 9, 2023Inventors: Tao WEI, Yonghong TIAN, Yaowei WANG, Yun LIANG, Chang Wen CHEN, Wen GAO
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Patent number: 11551968Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.Type: GrantFiled: September 23, 2020Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Wen Hsueh, Jiing-Feng Yang, Chii-Ping Chen, Po-Hsiang Huang, Chang-Wen Chen, Cai-Ling Wu
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Publication number: 20220359266Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Hsiu-Wen Hsueh, Jiing-Feng Yang, Chii-Ping Chen, Po-Hsiang Huang, Chang-Wen Chen, Cai-Ling Wu
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Publication number: 20220359263Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.Type: ApplicationFiled: July 22, 2021Publication date: November 10, 2022Inventors: Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
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Publication number: 20220336269Abstract: A method according to the present disclosure includes receiving a workpiece that includes a first source/drain feature, a first dielectric layer over the first source/drain feature, and a source/drain contact disposed in the first dielectric layer and over the first source/drain feature. The method further includes depositing a second dielectric layer over the source/drain contact and the first dielectric layer, forming a source/drain contact via opening through the second dielectric layer to expose the source/drain contact, depositing a sacrificial plug in the source/drain contact via opening, depositing a third dielectric layer over the second dielectric layer and the sacrificial plug, forming a trench in the third dielectric layer to expose the sacrificial plug, removing the sacrificial plug to expose the source/drain contact via opening, and after the removing of the sacrificial plug, forming an integrated conductive feature into the trench and the exposed source/drain contact via opening.Type: ApplicationFiled: July 29, 2021Publication date: October 20, 2022Inventors: Ya-Ching Tseng, Chang-Wen Chen, Po-Hsiang Huang
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Publication number: 20220013407Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hsin Chan, Jiing-Feng Yang, Kuan-Wei Huang, Meng-Shu Lin, Yu-Yu Chen, Chia-Wei Wu, Chang-Wen Chen, Wei-Hao Lin, Ching-Yu Chang
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Publication number: 20210335655Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.Type: ApplicationFiled: September 23, 2020Publication date: October 28, 2021Inventors: Hsiu-Wen Hsueh, Jiing-Feng Yang, Chii-Ping Chen, Po-Hsiang Huang, Chang-Wen Chen, Cai-Ling Wu
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Patent number: 10432270Abstract: A multiplexed space-time block coding (M-STBC) scheme is described that allows for transmitting a single multicast transmission in a heterogeneous MIMO (i.e., multiple-input and multiple-output) environment, where receivers with fewer antennas can receive a lower resolution version of the multi-cast transmission, while receivers with a greater number of antennas can receive a higher resolution version of the multi-cast transmission. Thus, the M-STBC scheme allows for transmitting the single multicast transmission that includes both a spatial multiplexing mode and a diversity mode.Type: GrantFiled: November 11, 2013Date of Patent: October 1, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Chong Luo, Hao Cui, Chang Wen Chen, Feng Wu
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Patent number: 9824486Abstract: A method and system is proposed to create a generative model to interpolate any view of a planar scene given a sequence of reference views and a synthesis view that is optimized by the marginalization of photometric regulation, and geometric registration parameters. According to one aspect of the claimed subject matter, a technique is proposed to combine information from varying input camera poses. Planar homography based image super resolution in free view interpolation for planar structure is applied to the combined information. Non-redundant information is combined in such a manner that the high resolution and free view problems in traditional 2D based image-based rendering techniques are overcome.Type: GrantFiled: December 16, 2014Date of Patent: November 21, 2017Assignee: Futurewei Technologies, Inc.Inventors: Jie Hu, Chang Wen Chen, Dongqing Zhang, Hong Heather Yu
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Patent number: 9432056Abstract: Multi-level symbols generated by applying a Random Projection Code (RPC) to a source bit sequence are received at a receiver via a noisy channel. The received multi-level symbols are represented in a bipartite graph as constraint nodes connected via weighted edges to binary variable nodes that represent the source bit sequence. A decoder uses ZigZag deconvolution to generate constraint node messages as part of an iterative belief propagation to decode the source bit sequence from the received multi-level symbols.Type: GrantFiled: November 4, 2013Date of Patent: August 30, 2016Assignee: Microsoft Technology Licensing, LLCInventors: Chong Luo, Hao Cui, Feng Wu, Chang Wen Chen
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Patent number: 9431613Abstract: A method of fabricating a perovskite solar cell includes forming a hole transport layer on a transparent electrically conductive substrate, and forming a perovskite layer on the hole transport layer via a two-stage vacuum evaporation process. Then, an electron transport layer and an electrode layer are formed in order. The two-stage vacuum evaporation process includes first vacuum evaporating a first material on the hole transport layer and then vacuum evaporating a second material on the first material so as to react the first material with the second material in situ and form the perovskite layer.Type: GrantFiled: January 21, 2015Date of Patent: August 30, 2016Assignee: National Tsing Hua UniversityInventors: Hao-Wu Lin, Chang-Wen Chen, Hao-Wei Kang, Sheng-Yi Hsiao
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Publication number: 20160049585Abstract: A method of fabricating a perovskite solar cell includes forming a hole transport layer on a transparent electrically conductive substrate, and forming a perovskite layer on the hole transport layer via a two-stage vacuum evaporation process. Then, an electron transport layer and an electrode layer are formed in order. The two-stage vacuum evaporation process includes first vacuum evaporating a first material on the hole transport layer and then vacuum evaporating a second material on the first material so as to react the first material with the second material in situ and form the perovskite layer.Type: ApplicationFiled: January 21, 2015Publication date: February 18, 2016Inventors: Hao-Wu Lin, Chang-Wen Chen, Hao-Wei Kang, Sheng-Yi Hsiao
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Publication number: 20150170405Abstract: A method and system is proposed to create a generative model to interpolate any view of a planar scene given a sequence of reference views and a synthesis view that is optimized by the marginalization of photometric regulation, and geometric registration parameters. According to one aspect of the claimed subject matter, a technique is proposed to combine information from varying input camera poses. Planar homography based image super resolution in free view interpolation for planar structure is applied to the combined information. Non-redundant information is combined in such a manner that the high resolution and free view problems in traditional 2D based image-based rendering techniques are overcome.Type: ApplicationFiled: December 16, 2014Publication date: June 18, 2015Inventors: Jie HU, Chang Wen CHEN, Dongqing ZHANG, Hong Heather YU
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Publication number: 20150131720Abstract: A multiplexed space-time block coding (M-STBC) scheme is described that allows for transmitting a single multicast transmission in a heterogeneous MIMO (i.e., multiple-input and multiple-output) environment, where receivers with fewer antennas can receive a lower resolution version of the multi-cast transmission, while receivers with a greater number of antennas can receive a higher resolution version of the multi-cast transmission. Thus, the M-STBC scheme allows for transmitting the single multicast transmission that includes both a spatial multiplexing mode and a diversity mode.Type: ApplicationFiled: November 11, 2013Publication date: May 14, 2015Applicant: Microsoft CorporationInventors: Chong Luo, Hao Cui, Chang Wen Chen, Feng Wu
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Publication number: 20150124908Abstract: Multi-level symbols generated by applying a Random Projection Code (RPC) to a source bit sequence are received at a receiver via a noisy channel. The received multi-level symbols are represented in a bipartite graph as constraint nodes connected via weighted edges to binary variable nodes that represent the source bit sequence. A decoder uses ZigZag deconvolution to generate constraint node messages as part of an iterative belief propagation to decode the source bit sequence from the received multi-level symbols.Type: ApplicationFiled: November 4, 2013Publication date: May 7, 2015Applicant: Microsoft CorporationInventors: Chong Luo, Hao Cui, Feng Wu, Chang Wen Chen
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Patent number: 8971433Abstract: A projection code is applied to encode symbols as weighted arithmetic sums of approximately random subsets of binary source bits. Pairs of the symbols are combined to form constellation points, which are sequentially mapped through a constellation to modulate a data signal.Type: GrantFiled: November 12, 2010Date of Patent: March 3, 2015Assignee: Microsoft Technology Licensing LLCInventors: Chong Luo, Kun Tan, Feng Wu, Hao Cui, Chang Wen Chen
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Publication number: 20140354768Abstract: A system, method or computer readable storage device to enable mobile devices in capturing high quality photos by using both the rich context available from mobile devices and crowd-sourced social media on the Web. Considering the flexible and adaptive adoption of photography principles with different content and context composition rules and exposure principles are learned from the community-contributed images. Leveraging a mobile device user's scene context and social context, the proposed socialized mobile photography system is able to suggest optimal view enclosure to achieve appealing composition. Due to the complex scene content and a number of shooting-related contexts to exposure parameters, exposure learning is applied to suggest appropriate camera parameters.Type: ApplicationFiled: May 30, 2013Publication date: December 4, 2014Inventors: Tao Mei, Shipeng Li, Wenyuan Yin, Chang Wen Chen
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Patent number: 8687530Abstract: Described is a technology by which a roadside-to-vehicle communication system may be implemented, including via a stateful scheduling with network coding scheme that enhances network capacity. Moving vehicles request and receive data from a roadside access points. Each of the access points operate a stateful scheduling algorithm that serves multiple vehicles by integrating network coding within a timeslot. In one aspect, the state of each vehicle's previously received and retained data is obtained, and used to enhance network capacity by combining as many packets as possible for multiple recipients in network coding.Type: GrantFiled: May 9, 2008Date of Patent: April 1, 2014Assignee: Microsoft CorporationInventors: Chong Luo, Han Cheng Lu, Wei Pu, Feng Wu, Chang Wen Chen
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Publication number: 20120121030Abstract: A projection code is applied to encode symbols as weighted arithmetic sums of approximately random subsets of binary source bits. Pairs of the symbols are combined to form constellation points, which are sequentially mapped through a constellation to modulate a data signal.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: Microsoft CorporationInventors: Chong Luo, Kun Tan, Feng Wu, Hao Cui, Chang Wen Chen