Abstract: Disclosed herein is a method of printing a nanostructure including: preparing a template substrate on which a pattern is formed; forming a replica pattern having an inverse phase of the pattern by coating a polymer thin film on an upper portion of the template substrate, adhering a thermal release tape to an upper portion of the polymer thin film, and separating the polymer thin film from the template substrate; forming a nanostructure by depositing a functional material on the replica pattern; and printing the nanostructure deposited on the replica pattern to a substrate by positioning the nanostructure on the substrate, applying heat and pressure to the nanostructure, and weakening an adhesive force between the thermal release tape and the replica pattern by the heat.

Abstract: Disclosed herein is a method of depositing a transition metal single-atom catalyst including preparing a carbon carrier, and depositing a transition metal single-atom catalyst on the carbon carrier, in which the carbon carrier is surface-treated by an oxidation process, and wherein the deposition is carried out by an arc plasma process.

Abstract: A thermoelectric module includes; an upper substrate on which a plurality of upper electrodes having a plurality of first concave grooves formed therein are arranged, a lower substrate, on which a plurality of lower electrodes having a plurality of second concave grooves formed therein are arranged, and a least one spherical p-type thermoelectric element and at least one spherical n-type thermoelectric element interposed between the upper substrate and the lower substrate, and electrically and alternately in contact with the upper substrate and the lower substrate, wherein the at least one spherical p-type thermoelectric element and the at least one spherical n-type thermoelectric element are connected to the plurality of first concave grooves and the plurality of second concave grooves respectively disposed in the upper electrodes and the lower electrodes.

Abstract: A thin film transistor (TFT) array panel includes: an insulating substrate (110); first and second semiconductor members (151 a,b) formed on the substrate and having opposite conductivity; a first gate member (121a) formed on a first layer (140), insulated from the first and the second semiconductor members and overlapping one of the first and the second semiconductor members; a second gate member (122a) formed on the first layer (140), separated from the first gate member, and insulated from the first and the second semiconductor members (151 a,b), the second gate member (122a) not overlapping the first and the second semiconductor members; a first data member (162) formed on a second layer (160), connected to one of the first and the second semiconductor members (151 a,b) and insulated from the first (121a) and the second (122a) gate members; and a first connection (123) formed on the second layer (160) and connecting the first gate member (121a) and the second gate member (122a).

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A thin film transistor array panel includes: an insulating substrate (110); first and second semiconductor members (151 a,b) formed on the substrate and having opposite conductivity; a first gate member (121a) insulated from the first and the second semiconductor members and overlapping one of the first and the second semiconductor members; a second gate member (122a) formed on the same layer as the first gate member (121a), separated from the first gate member, and insulated from the first and the second semiconductor members (151 a,b), the second gate member (122a) not overlapping the first and the second semiconductor members; a first data member (162) connected to one of the first and the second semiconductor members (151 a,b) and insulated from the first (121a) and the second (122a) gate members; and a first connection (123) formed on the same layer as the first data member and connecting the first gate member (121a) and the second gate member (122a).

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: In a TFT LCD device comprising a substrate, at least one thin film transistor formed on the substrate, having a source electrode and a drain electrode, an insulating layer formed over the whole surface of the substrate on which the thin film transistor is formed, having at least one contact hole exposing a portion of the drain electrode, and reflective layer pixel electrode corresponding to the thin film transistor, formed on the insulating layer to be connected with the drain electrode through the contact hole, the pixel electrode is formed of a multi-layered conductive layer. The drain electrode is composed of multiple layers, and the most upper layer of the multiple layers is one selected from a Cr layer and a MoW layer. Preferably, the multi-layered conductive layer is composed of two-layered conductive layer having a lower layer of the same material as that of the most upper layer and an upper layer of Al-containing metal.

Abstract: A polycrystalline silicon TFT for an LCD and a manufacturing method thereof is disclosed. The TFT comprises an active pattern formed on a substrate, a gate insulating layer formed on the substrate including the active pattern, a gate line formed on the gate insulating layer to be crossed with the active pattern and including a gate electrode for defining the first impurity region, a second impurity region and a channel region, an insulating interlayer formed on the gate insulating layer including the gate line, a data line formed on the insulating interlayer and connected to the second impurity region through the first contact hole which is formed through the gate insulating layer and the insulating interlayer on the second impurity region and a pixel electrode formed on the same insulating interlayer as the data line and connected with the first impurity region through a second contact hole which is formed through the gate insulating layer and the insulating interlayer on the first impurity region.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: A polycrystalline silicon TFT for an LCD and a manufacturing method thereof is disclosed. The TFT comprises an active pattern formed on a substrate, a gate insulating layer formed on the substrate including the active pattern, a gate line formed on the gate insulating layer to be crossed with the active pattern and including a gate electrode for defining the first impurity region, a second impurity region and a channel region, an insulating interlayer formed on the gate insulating layer including the gate line, a data line formed on the insulating interlayer and connected to the second impurity region through the first contact hole which is formed through the gate insulating layer and the insulating interlayer on the second impurity region and a pixel electrode formed on the same insulating interlayer as the data line and connected with the first impurity region through a second contact hole which is formed through the gate insulating layer and the insulating interlayer on the first impurity region.

Abstract: In a TFT LCD device comprising a substrate, at least one thin film transistor formed on the substrate, having a source electrode and a drain electrode, an insulating layer formed over the whole surface of the substrate on which the thin film transistor is formed, having at least one contact hole exposing a portion of the drain electrode, and reflective layer pixel electrode corresponding to the thin film transistor, formed on the insulating layer to be connected with the drain electrode through the contact hole, the pixel electrode is formed of a multi-layered conductive layer. The drain electrode is composed of multiple layers, and the most upper layer of the multiple layers is one selected from a Cr layer and a MoW layer. Preferably, the multi-layered conductive layer is composed of two-layered conductive layer having a lower layer of the same material as that of the most upper layer and an upper layer of Al-containing metal.

Abstract: A double level gate layer with an undercut lower gate layer can be formed by using the etching rate difference between the upper gate layer and the lower gate layer in a polycrystalline Si type TFT LCD that has P-channel TFTs and N-channel TFTs. An LDD structure can be easily formed by using an upper gate layer as ion implant mask during the N-type ion implantation. LDD size is decided by the skew size between the upper gate layer and the lower gate layer. Furthermore, a photolithography step necessary for masking the ion implantation can be skipped.

Abstract: A source electrode and a metal pattern for a storage capacitor are formed on an insulating substrate, a silicon layer having a doped source region and a doped drain region is formed on the substrate and the source and the drain regions directly contact to the source electrode and the metal pattern. A gate insulating film is formed thereon, and a storage electrode is formed on the gate insulating film opposite the metal pattern. A passivation film covering the storage electrode is formed and the pixel electrode is formed thereon. The pixel electrode is directly connected to the drain region or to the metal pattern.

Abstract: The present invention is related to the method of forming thin film transistor that can be used for flat display devices wherein a method of making TFT for display devices have the steps of, forming subsidiary conductor patterns connecting plurality of electrically isolated conductor patterns, implanting impurity ions utilizing the conductor patterns and subsidiary conductor patterns as implantation mask and removing the subsidiary conductor patterns.

Abstract: In a TFT LCD device comprising a substrate, at least one thin film transistor formed on the substrate, having a source electrode and a drain electrode, an insulating layer formed over the whole surface of the substrate on which the thin film transistor is formed, having at least one contact hole exposing a portion of the drain electrode, and reflective layer pixel electrode corresponding to the thin film transistor, formed on the insulating layer to be connected with the drain electrode through the contact hole, the pixel electrode is formed of a multi-layered conductive layer. The drain electrode is composed of multiple layers, and the most upper layer of the multiple layers is one selected from a Cr layer and a MoW layer. Preferably, the multi-layered conductive layer is composed of two-layered conductive layer having a lower layer of the same material as that of the most upper layer and an upper layer of Al-containing metal.