Patents by Inventor Chang-Woo SOHN
Chang-Woo SOHN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210111270Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.Type: ApplicationFiled: February 24, 2020Publication date: April 15, 2021Inventors: CHANG WOO SOHN, SEUNG HYUN SONG, SEON-BAE KIM, MIN CHEOL OH, YOUNG CHAI JUNG
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Publication number: 20200357920Abstract: A vertical field-effect transistor (VFET) device and a method of manufacturing the same are provided. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure, and a conductor layer formed on a lower portion of the gate dielectric layer; a top source/drain (S/D) region formed above the fin structure and the gate structure; a bottom S/D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.Type: ApplicationFiled: March 24, 2020Publication date: November 12, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Hyun SONG, Chang Woo SOHN, Young Chai JUNG, Sa Hwan HONG
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Publication number: 20200343341Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jung Gil YANG, Dong Il BAE, Chang Woo SOHN, Seung Min SONG, Dong Hun LEE
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Patent number: 10756179Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: GrantFiled: May 28, 2019Date of Patent: August 25, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Gil Yang, Dong Il Bae, Chang Woo Sohn, Seung Min Song, Dong Hun Lee
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Publication number: 20190296107Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: ApplicationFiled: May 28, 2019Publication date: September 26, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Jung Gil YANG, Dong II BAE, Chang Woo SOHN, Seung Min SONG, Dong Hun LEE
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Patent number: 10403717Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.Type: GrantFiled: August 25, 2017Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
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Patent number: 10347718Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: GrantFiled: January 23, 2018Date of Patent: July 9, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jung Gil Yang, Dong Il Bae, Chang Woo Sohn, Seung Min Song, Dong Hun Lee
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Patent number: 10242917Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.Type: GrantFiled: June 27, 2017Date of Patent: March 26, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Woo Kim, Shigenobu Maeda, Young-Moon Choi, Yong-Bum Kwon, Chang-Woo Sohn, Do-Sun Lee
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Publication number: 20180158908Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: ApplicationFiled: January 23, 2018Publication date: June 7, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Jung Gil YANG, Dong II BAE, Chang Woo SOHN, Seung Min SONG, Dong Hun LEE
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Publication number: 20180090569Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: ApplicationFiled: March 20, 2017Publication date: March 29, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Jung Gil YANG, Dong ll BAE, Chang Woo SOHN, Seung Min SONG, Dong Hun LEE
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Patent number: 9929235Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.Type: GrantFiled: March 20, 2017Date of Patent: March 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Gil Yang, Dong Il Bae, Chang Woo Sohn, Seung Min Song, Dong Hun Lee
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Publication number: 20170352728Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
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Patent number: 9793381Abstract: A method for manufacturing a semiconductor device includes forming a fin structure extending in a first direction on a substrate, forming a sacrificial gate pattern extending in a second direction to intersect the fin structure, forming a gate spacer layer covering the fin structure and the sacrificial gate pattern, providing a first ion beam having a first incident angle range and a second ion beam having a second incident angle range to the substrate, patterning the gate spacer layer using the first ion beam and the second ion beam to form gate spacers on sidewalls of the sacrificial gate pattern, forming source/drain regions at both sides of the sacrificial gate patterns, and replacing the sacrificial gate pattern with a gate electrode.Type: GrantFiled: April 18, 2016Date of Patent: October 17, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kyungin Choi, Dongwoo Kim, Chang Woo Sohn, Youngmoon Choi
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Publication number: 20170294355Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.Type: ApplicationFiled: June 27, 2017Publication date: October 12, 2017Inventors: Dong-Woo KIM, Shigenobu Maeda, Young-Moon Choi, Yong-Bum Kwon, Chang-Woo Sohn, Do-Sun Lee
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Patent number: 9768255Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.Type: GrantFiled: January 26, 2016Date of Patent: September 19, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
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Patent number: 9728601Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.Type: GrantFiled: March 2, 2016Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Woo Kim, Shigenobu Maeda, Young-Moon Choi, Yong-Bum Kwon, Chang-Woo Sohn, Do-Sun Lee
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Publication number: 20160359020Abstract: A method for manufacturing a semiconductor device includes forming a fin structure extending in a first direction on a substrate, forming a sacrificial gate pattern extending in a second direction to intersect the fin structure, forming a gate spacer layer covering the fin structure and the sacrificial gate pattern, providing a first ion beam having a first incident angle range and a second ion beam having a second incident angle range to the substrate, patterning the gate spacer layer using the first ion beam and the second ion beam to form gate spacers on sidewalls of the sacrificial gate pattern, forming source/drain regions at both sides of the sacrificial gate patterns, and replacing the sacrificial gate pattern with a gate electrode.Type: ApplicationFiled: April 18, 2016Publication date: December 8, 2016Inventors: Kyungin CHOI, Dongwoo KIM, Chang Woo SOHN, Youngmoon CHOI
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Publication number: 20160308004Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.Type: ApplicationFiled: January 26, 2016Publication date: October 20, 2016Inventors: Do-Sun LEE, Chang-Woo SOHN, Chul-Sung KIM, Shigenobu MAEDA, Young-Moon CHOI, Hyo-Seok CHOI, Sang-Jin HYUN
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Publication number: 20160293697Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.Type: ApplicationFiled: March 2, 2016Publication date: October 6, 2016Inventors: Dong-Woo KIM, Shigenobu MAEDA, Young-Moon CHOI, Yong-Bum KWON, Chang-Woo SOHN, Do-Sun LEE