Abstract: A variable resistance memory device may include a plurality of stacked structures. Each of the stacked structures may be formed on a substrate, and may include a lower electrode, a variable resistance pattern and a selection pattern sequentially stacked. A threshold voltage control pattern may be formed on the stacked structures, may extend in a second direction parallel to an upper surface of the substrate and may be configured to either increase or decrease a threshold voltage of each selection pattern. An upper electrode may be formed on the threshold voltage control pattern and may extend in the second direction. A first conductive line may contact respective lower surfaces of the lower electrodes of the stacked structures and extend in a first direction perpendicular to the second direction. A second conductive line may contact an upper surface of the upper electrode and extend in the second direction.

Abstract: An organometallic precursor includes tungsten as a central metal and a cyclopentadienyl ligand bonded to the central metal. A first structure including an alkylsilyl group or a second structure including an allyl ligand is bonded to the cyclopentadienyl ligand or bonded to the central metal.

Abstract: A semiconductor device is provided including a base insulating layer on a substrate; a first conductive line that extends in a first direction on the base insulating layer; data storage structures on the first conductive line; selector structures on the data storage structures, each of the selector structures including a lower selector electrode, a selector, and an upper selector electrode; an insulating layer in a space between the selector structures; and a second conductive line disposed on the selector structures and the insulating layer and extended in a second direction intersecting the first direction. An upper surface of the insulating layer is higher than an upper surface of the upper selector electrode.

Abstract: A variable resistance memory device may include a plurality of stacked structures. Each of the stacked structures may be formed on a substrate, and may include a lower electrode, a variable resistance pattern and a selection pattern sequentially stacked. A threshold voltage control pattern may be formed on the stacked structures, may extend in a second direction parallel to an upper surface of the substrate and may be configured to either increase or decrease a threshold voltage of each selection pattern. An upper electrode may be formed on the threshold voltage control pattern and may extend in the second direction. A first conductive line may contact respective lower surfaces of the lower electrodes of the stacked structures and extend in a first direction perpendicular to the second direction. A second conductive line may contact an upper surface of the upper electrode and extend in the second direction.

Abstract: An organometallic precursor includes tungsten as a central metal and a cyclopentadienyl ligand bonded to the central metal. A first structure including an alkylsilyl group or a second structure including an allyl ligand is bonded to the cyclopentadienyl ligand or bonded to the central metal.

Abstract: An organometallic precursor includes tungsten as a central metal and a cyclopentadienyl ligand bonded to the central metal. A first structure including an alkylsilyl group or a second structure including an allyl ligand is bonded to the cyclopentadienyl ligand or bonded to the central metal.

Abstract: A semiconductor device is provided including a base insulating layer on a substrate; a first conductive line that extends in a first direction on the base insulating layer; data storage structures on the first conductive line; selector structures on the data storage structures, each of the selector structures including a lower selector electrode, a selector, and an upper selector electrode; an insulating layer in a space between the selector structures; and a second conductive line disposed on the selector structures and the insulating layer and extended in a second direction intersecting the first direction. An upper surface of the insulating layer is higher than an upper surface of the upper selector electrode.

Abstract: An organometallic precursor includes tungsten as a central metal and a cyclopentadienyl ligand bonded to the central metal. A first structure including an alkylsilyl group or a second structure including an allyl ligand is bonded to the cyclopentadienyl ligand or bonded to the central metal.

Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.

Abstract: A method of manufacturing magnetoresistive random access memory (MRAM) device includes forming first and second patterns on a substrate in an alternating and repeating arrangement, forming a first capping layer on top surfaces of the first and second patterns, and removing first portions of the first capping layer and a portion of the second patterns thereunder to form first openings exposing the substrate. The method further includes forming source lines filling lower portions of the first openings, respectively, forming second capping layer patterns filling upper portions of the first openings, respectively, and removing second portions of the first capping layer and a portion of the second patterns thereunder to form second openings exposing the substrate. Then, contact plugs and pad layers are integrally formed and sequentially stacked on the substrate to fill the second openings.

Abstract: In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.

Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.

Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.

Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.

Abstract: A method of manufacturing magnetoresistive random access memory (MRAM) device includes foaming first and second patterns on a substrate in an alternating and repeating arrangement, forming a first capping layer on top surfaces of the first and second patterns, and removing first portions of the first capping layer and a portion of the second patterns thereunder to form first openings exposing the substrate. The method further includes forming source lines filling lower portions of the first openings, respectively, forming second capping layer patterns filling upper portions of the first openings, respectively, and removing second portions of the first capping layer and a portion of the second patterns thereunder to form second openings exposing the substrate. Then, contact plugs and pad layers are integrally formed and sequentially stacked on the substrate to fill the second openings.

Abstract: In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.

Abstract: Methods of fabricating vertical memory devices are provided including forming a plurality of alternating insulating layers and sacrificial layers on a substrate; patterning and etching the plurality of insulating layer and sacrificial layers to define an opening that exposes at least a portion of a surface of the substrate; forming a charge trapping pattern and a tunnel insulating pattern on a side wall of the opening; forming a channel layer on the tunnel insulating layer on the sidewall of the opening, the channel layer including N-type impurity doped polysilicon; forming a buried insulating pattern on the channel layer in the opening; and forming a blocking dielectric layer and a control gate on the charge trapping pattern of one side wall of the channel layer.

Abstract: A semiconductor device includes a channel region extending in a vertical direction perpendicular to a substrate and having a nitrogen concentration distribution, a plurality of gate electrodes arranged on a side wall of the channel region and separated from each other in a vertical direction, and a gate dielectric layer disposed between the channel region and the gate electrodes. The nitrogen concentration distribution has a first concentration near an interface between the channel region and the gate dielectric layer.

Abstract: An authentication apparatus includes a data storage unit for storing authentication apparatus identification information, an interface unit for connecting to a host device through a first interface, and an authentication processor that executes an authentication process using the authentication apparatus identification information stored in the data storage unit. The authentication processor executes the authentication process upon receipt of an authentication request signal from the host device through the interface unit, and outputs an authentication response signal including data indicative of a result of the authentication process to the host device via the interface unit. The authentication request signal is for requesting authentication of a data storage device connected to the host device through a second interface.