Patents by Inventor Chang-Yao Hsieh

Chang-Yao Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9831303
    Abstract: A process for fabricating a capacitor is described. A template layer including a stack of at least one first layer and at least one second layer is formed over a substrate, wherein the at least one first layer and the at least one second layer have different etching selectivities and are arranged alternately. An opening is formed through the template layer. A wet etching process is performed to recess the at least one first layer relative to the at least one second layer, at the sidewall of the opening. A bottom electrode of the capacitor is formed at the bottom of the opening and on the sidewall of the opening, and then the template layer is removed.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: November 28, 2017
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chi-Hsiang Kuo, Cheng-Shun Chen, Chang-Yao Hsieh
  • Publication number: 20140126105
    Abstract: A process for fabricating a capacitor is described. A template layer including a stack of at least one first layer and at least one second layer is formed over a substrate, wherein the at least one first layer and the at least one second layer have different etching selectivities and are arranged alternately. An opening is formed through the template layer. A wet etching process is performed to recess the at least one first layer relative to the at least one second layer, at the sidewall of the opening. A bottom electrode of the capacitor is formed at the bottom of the opening and on the sidewall of the opening, and then the template layer is removed.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Inventors: Chi-Hsiang Kuo, Cheng-Shun Chen, Chang-Yao Hsieh
  • Publication number: 20100233881
    Abstract: A method of manufacturing a supporting structure for a stack capacitor in a semiconductor device is provided. The method includes the following steps. The first step is providing a multi-layer structure including an etching stop layer, a silicon oxide layer and a silicon nitride layer. The second step is etching the silicon nitride layer and the silicon oxide layer to form a plurality of filling recesses in the silicon oxide layer, in which each the filling recess has a lateral surface and a bottom surface. The third step is forming a protecting layer at each the lateral surface. The fourth step is etching the silicon oxide layer to expose the etching stop layer. The fifth step is removing the protecting layer on the each lateral surface, thereby forming the supporting structure.
    Type: Application
    Filed: June 26, 2009
    Publication date: September 16, 2010
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Chung-Chiang Min, Chang-Yao Hsieh