Patents by Inventor Chang-Yi Lan

Chang-Yi Lan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10224243
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: March 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • Publication number: 20180138158
    Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Shu-Huei Huang
  • Publication number: 20180068896
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Application
    Filed: September 14, 2017
    Publication date: March 8, 2018
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • Patent number: 9905546
    Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Huei Huang
  • Patent number: 9805979
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: October 31, 2017
    Assignee: Siliconware Precision Industires Co., Ltd.
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • Publication number: 20160133593
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Application
    Filed: February 18, 2015
    Publication date: May 12, 2016
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • Patent number: 9112063
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 18, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Publication number: 20150187741
    Abstract: A method for fabricating a package on package (PoP) structure is provided, which includes: providing a first packaging substrate having at least a first electronic element and a plurality of first support portions, wherein the first electronic element is electrically connected to the first packaging substrate; forming an encapsulant on the first packaging substrate for encapsulating the first electronic element and the first support portions; forming a plurality of openings in the encapsulant for exposing portions of surfaces of the first support portions; and providing a second packaging substrate having a plurality of second support portions and stacking the second packaging substrate on the first packaging substrate with the second support portions positioned in the openings of the encapsulant and bonded with the first support portions. As such, the encapsulant effectively separates the first support portions or the second support portions from one another to prevent bridging from occurring therebetween.
    Type: Application
    Filed: March 14, 2014
    Publication date: July 2, 2015
    Applicant: Siliconware Precision Industries Co., Ltd
    Inventors: Shih-Hao Tung, Chang-Yi Lan, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Huei Huang
  • Publication number: 20140308780
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Patent number: 8796867
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: August 5, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Publication number: 20130307152
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
    Type: Application
    Filed: August 17, 2012
    Publication date: November 21, 2013
    Inventors: Wei Chung Hsiao, Chun Hsien Lin, Yu Cheng Pai, Liang Yi Hung, Ming Chen Sun, Shao Tzu Tang, Ying Chou Tsai, Chang Yi Lan
  • Publication number: 20130292832
    Abstract: A semiconductor package includes: a first insulating layer; a plurality of first conductive elements disposed in the first insulating layer; a first circuit layer formed on the first insulating layer; a semiconductor chip disposed on the first insulating layer; and an encapsulant formed on the first insulating layer and encapsulating the semiconductor chip. The first conductive elements that are bonding wires have a small diameter and thus occupy desired limited space on the first insulating layer. Therefore, more space is available for the first circuit layer.
    Type: Application
    Filed: August 14, 2012
    Publication date: November 7, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shao-Tzu Tang, Chi-Ching Ho, Ying-Chou Tsai, Chang-Yi Lan