Patents by Inventor Chang Ying Hung

Chang Ying Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8541883
    Abstract: The present invention relates to a semiconductor device having a shielding layer. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: September 24, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hung-Hsiang Cheng, Tzu-Chih Lin, Chang-Ying Hung, Chih-Wei Wu
  • Publication number: 20130134601
    Abstract: The present invention relates to a semiconductor device having a shielding layer and a method for making the same. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hung-Hsiang Cheng, Tzu-Chih Lin, Chang-Ying Hung, Chih-Wei Wu
  • Patent number: 8110931
    Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: February 7, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian Cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
  • Patent number: 8076786
    Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: December 13, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang Ying Hung, Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Jian Cheng Chen, Wei Chi Yih, Ho Ming Tong
  • Patent number: 8053906
    Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: November 8, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian Cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Tsung Hsu, Chih Cheng Hung
  • Patent number: 8018075
    Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: September 13, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian Cheng Chen, Wei Chi Yih, Chang Ying Hung
  • Publication number: 20100200974
    Abstract: A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element.
    Type: Application
    Filed: July 17, 2009
    Publication date: August 12, 2010
    Inventors: Chao-Fu Weng, Tsung-Yueh Tsai, Chang-Ying Hung, Jen-Chieh Kao
  • Publication number: 20100007010
    Abstract: A wire bonding structure of a semiconductor package includes a bonding wire, a pad and a non-conductive adhesive material. The bonding wire includes a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the sectional area of the block portion is bigger than that of the line portion. The pad is bonded to the block portion. The non-conductive adhesive material covers the pad and seals the whole block portion of the bonding wire.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiao Chuan CHANG, Tsung Yueh TSAI, Yi Shao LAI, Ho Ming TONG, Jian Cheng CHEN, Wei Chi YIH, Chang Ying HUNG
  • Publication number: 20100007004
    Abstract: A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsiao Chuan CHANG, Tsung Yueh Tsai, Yi Shao Lai, Ho Ming Tong, Jian cheng Chen, Wei Chi Yih, Chang Ying Hung, Cheng Wei Huang, Chih Hsing Chen, Tai Yuan Huang, Chieh Ting Chen, Yi Tsai Lu
  • Publication number: 20100007009
    Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Hsiao Chuan CHANG, Tsung Yueh TSAI, Yi Shao LAI, Ho Ming TONG, Jian Cheng CHEN, Wei Chi YIH, Chang Ying HUNG, Cheng Tsung HSU, Chih Cheng HUNG
  • Publication number: 20100007011
    Abstract: A wire bonding structure includes a chip and a bonding wire. The chip includes a base material, at least one first metallic pad, a re-distribution layer and at least one second metallic pad. The first metallic pad is disposed on the base material. The re-distribution layer has a first end and a second end, and the first end is electrically connected to the first metallic pad. The second metallic pad is electrically connected to the second end of the re-distribution layer. The bonding wire is bonded to the second metallic pad.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 14, 2010
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Ying HUNG, Hsiao Chuan Chang, Tsung Yueh Tsai, Yi Shao Lai, Jian Cheng Chen, Wei Chi Yih, Ho Ming Tong