Abstract: Provided is an active matrix electroluminescent display apparatus in which a short circuit between a power line and data line in adjacent sub-pixels can be substantially prevented. The active matrix electroluminescent display apparatus includes: a power line; a first transistor positioned on a side of the power line and connected to the power line; a second transistor positioned on the other side of the power line and connected to the power line; and electroluminescent devices respectively connected to the first transistor and the second transistor.

Abstract: A display device according to an exemplary embodiment of the present invention includes a display portion including a plurality of display pixels displaying an image and a dummy portion including a plurality of dummy pixels formed in a periphery region of the display portion. An electrostatic test element group (TEG) may be formed in at least one of the dummy pixels.

Abstract: A display device includes: a base film including plastic; an active layer on the base film, the active layer including a polysilicon layer formed by crystallizing an amorphous silicon layer using a laser; a barrier layer between the active layer and the base film; and a laser absorption layer between the barrier layer and the active layer.

Abstract: A display device includes: a substrate having a bonding area at an edge of the substrate; a conductive pad on the bonding area of the substrate; an external connection member having a connection area bonded with the bonding area of the substrate; a bump in the connection area of the external connection member at a side of the external connection member facing the conductive pad; and an anisotropic conductive film selectively disposed between the conductive pad and the bump and forming an electrical connection between the conductive pad and the bump.

Abstract: An electroluminescent (EL) display device and a method of fabricating the same are provided. The device includes a substrate; a plurality of pixel electrodes disposed on the substrate; a pixel defining layer disposed on the pixel electrodes and having an opening part exposing a predetermined part of each of the pixel electrodes; and at least one barrier layer comprised in and/or on the pixel defining layer. In this device, the pixel defining layer includes at least one barrier layer in order to reduce the amount of outgas from the pixel defining layer and prevent degradation of an emission portion due to the outgas. Also, the pixel defining layer is formed to a sufficiently small thickness to facilitate a subsequent process using a laser induced thermal imaging (LITI) process.

Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Abstract: Provided is a flat display device having a display region in which more than one thin film transistor and more than one pixel are included. The device includes a driving line that supplies driving power to the display region, and an auxiliary driving line, which is coupled with the driving line, is formed in a different layer from the driving line. The driving line may be an identical layer to the source/drain electrodes of the display region.

Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Abstract: A pad area and a method of fabricating the same, wherein the pad area is formed on a substrate to contact a chip on glass (COG) or a chip on flexible printed circuit (COF) with the substrate. Changing a lower structure of the pad area increases contact points between conductive balls and an interconnection layer or reduces a step difference between an interconnection layer and a passivation layer to enhance and ensure electrical connection.

Abstract: An organic light emitting display and method of fabricating the same are provided. The organic light emitting display includes: a TFT disposed on a substrate and having a gate electrode and source and drain electrodes; a pixel electrode formed on a planarization layer having a via contact hole over the substrate, connected to one of the source and drain electrodes through the via contact hole, and having an etching surface extending to the planarization layer; a pixel defining layer pattern for defining an emission region formed on the entire surface; an organic layer formed on an emission region of the pixel electrode, and having at least an emission layer; and an opposite electrode formed on the entire surface, thereby preventing the organic layer from being separated from an edge of the pixel electrode and a short circuit from occurring between the pixel electrode and the opposite electrode to improve device characteristics and reliability.

Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.

Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.

Abstract: A TFT having a dual buffer structure, a method of fabricating the same, and a flat panel display having the TFT, and a method of fabricating the same are provided. The TFT includes a first buffer layer formed of an amorphous silicon layer on a substrate, a second buffer layer formed on the first buffer layer. The TFT also includes a semiconductor layer formed on the second buffer layer and a gate electrode formed on the semiconductor layer. The dual buffer structure provides better barrier to impurities diffusing from the substrate, and also acts as a black matrix to reduce unwanted reflections and is a source of hydrogen to passivate other layers.

Abstract: An organic light emitting display device (OLED) and a method of fabricating the same, in which electric field influence between first and second electrodes is reduced in an edge region of a unit pixel. The OLED includes a substrate, and a thin film transistor (TFT) located on the substrate. A passivation layer is located on the TFT over substantially an entire surface of the substrate, and has a via hole for exposing source or drain electrode, and a groove. A first electrode on the passivation layer is in electrical contact with the exposed source or drain electrode through the via hole, and has an edge located in the groove. A pixel defining layer is located on the first electrode and has an opening for exposing a predetermined portion of the first electrode. An organic layer is in contact with the predetermined portion, and a second electrode is formed on the organic layer.

Abstract: An electroluminescence display device including a thin film transistor layer formed on a substrate, at least one insulating layer, and a pixel layer that includes a first electrode layer, a second electrode layer, and an intermediate layer interposed between the first electrode layer and the second electrode layer and having at least an emitting layer. The pixel layer further includes a reflection layer that is disposed under the first electrode layer and that extends to a via hole formed in the insulating layer, and an auxiliary conductive layer is disposed under the reflection layer. The auxiliary conductive layer extends to the via hole, and the first electrode layer contacts at least a portion of the auxiliary conductive layer.

Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.

Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.

Abstract: A pad area and a method of fabricating the same, wherein the pad area is formed on a substrate to contact a chip on glass (COG) or a chip on flexible printed circuit (COF) with the substrate. Changing a lower structure of the pad area increases contact points between conductive balls and an interconnection layer or reduces a step difference between an interconnection layer and a passivation layer to enhance and ensure electrical connection.