Abstract: A method for training a model for face recognition is provided. The method forward trains a training batch of samples to form a face recognition model w(t), and calculates sample weights for the batch. The method obtains a training batch gradient with respect to model weights thereof and updates, using the gradient, the model w(t) to a face recognition model what(t). The method forwards a validation batch of samples to the face recognition model what(t). The method obtains a validation batch gradient, and updates, using the validation batch gradient and what(t), a sample-level importance weight of samples in the training batch to obtain an updated sample-level importance weight. The method obtains a training batch upgraded gradient based on the updated sample-level importance weight of the training batch samples, and updates, using the upgraded gradient, the model w(t) to a trained model w(t+1) corresponding to a next iteration.

Abstract: Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.

Abstract: A thin film transistor includes a bottom gate, a semiconductor layer, a top gate, a first auxiliary conductive pattern, a source, and a drain. The semiconductor layer includes a first semiconductor region, a second semiconductor region, a first heavily doped region, a second heavily doped region, a third heavily doped region, a first lightly doped region, a second lightly doped region, and a third lightly doped region. The first heavily doped region and the second heavily doped region are respectively located on two sides of the first semiconductor region. Two ends of the second semiconductor region are directly connected to the third heavily doped region and the third lightly doped region, respectively. The top gate is electrically connected to the bottom gate. The source and the drain are respectively electrically connected to the third heavily doped region and the second heavily doped region of the semiconductor layer.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: A transistor structure includes a substrate, a source electrode, a drain electrode, a protective layer and a gate electrode. The source electrode and the drain electrode are provided on the substrate. The protective layer is provided on the substrate. The protective layer is provided between the source electrode and the drain electrode. The protective layer includes a SiNx layer and a SiOx layer. The SiOx layer is provided on the substrate, the SiNx layer is provided on the SiOx layer, and a through hole of the protective layer is formed to extend through the SiNx layer and the SiOx layer. The gate electrode is provided in the through hole, and the gate electrode is separated from at least part of the SiOx layer so as to form an air gap therebetween.

Abstract: The present disclosure provides an electronic device including a first sensing circuit, a second sensing circuit and a power line. The first sensing circuit includes a first sensing unit and a first transistor, and a first end of the first sensing unit is coupled to a control end of the first transistor. The second sensing circuit includes a second sensing unit and a second transistor, and a first end of the second sensing unit is coupled to a control end of the second transistor. A first end of the first transistor and a first end of the second transistor are coupled to the power line.

Abstract: A light emitting display device includes a light emitting diode including a first electrode and a second electrode to which a driving voltage is applied, a driving transistor, a second transistor receiving a data voltage and connected to a D node, a storage capacitor connected to the driving transistor and an N node, a hold capacitor connected to the D node and the N node, a third transistor connected to the D node and the driving transistor, a fourth transistor receiving a reference voltage and connected to the driving transistor, a fifth transistor connected to the driving transistor and the N node, a sixth transistor receiving a driving low voltage and connected to the driving transistor, a seventh transistor receiving an initialization voltage and connected the driving transistor, and an eighth transistor connected to the driving transistor and the first electrode of the light emitting diode.

Abstract: A first planarization layer, an anode lap joint later, a pixel defining layer are between the first dam and the display area; the anode lap joint layer includes a main body portion and sharp angle portions; the sharp angle portion at least includes a first side edge close to the display area; the pixel defining layer wraps a border of the anode lap joint layer and has a first groove extending from one to the other sharp angle portion. An edge of the first groove adjacent to the first side edge of the sharp angle portion is a second side edge; and an orthographic projection of the second side edge on a base substrate is in an orthographic projection of the third groove on the base substrate.

Abstract: A memory device includes a memory array, a reference voltage generator and a driver circuit. The memory array includes a memory cell. The reference voltage generator is configured to generate a reference voltage based on a threshold voltage of a select transistor of the memory cell. The driver circuit is coupled to the reference voltage generator and is configured to generate at least one of a bit line voltage and a word line voltage according to the reference voltage, wherein the memory cell is driven by the at least one of the bit line voltage or the word line voltage, and the reference voltage generator comprises a resistor that is configured to sense the threshold voltage of the select transistor through a current flowing through the resistor.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: A scaling device of a real-time image and a scaling method are disclosed, the scaling device includes a storing unit, a receiving unit, a determining unit, a computing unit, and an outputting unit, wherein the storing unit stores multiple lookup tables respectively corresponding to different scaling algorithms. The receiving unit receives a real-time image from an image outputting device. The determining unit decides a scaling algorithm in accordance with the content of the real-time image and a required scaling ratio, and reads one of the lookup tables from the storing unit based on the decided scaling algorithm. The computing unit performs a scaling process on the real-time image to generate a processed image in accordance with the lookup table read by the determining unit. The outputting unit outputs the processed image.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: Embodiments of the application provide a sidelink logical channel multiplexing method and apparatus. After determining a first sidelink logical channel (SL LCH) that meets a first preset condition in at least one SL LCH, a terminal allocates a resource to data of the first SL LCH. Then, when a remaining resource of transmission resources is more than zero, the terminal determines, according to a communication range of the first SL LCH, a second SL LCH that meets a second preset condition, and allocates a resource to data of the second SL LCH. The first SL LCH and the second SL LCH are different. In the method, such a parameter as a communication range is considered in a multiplexing process, and data of SL LCHs with same or different communication ranges is multiplexed into a same transport block.

Abstract: A microscope device for observing a sample. The microscope device and the sample are located on an optical route. The microscope device includes an objective lens unit and an additional light source set. The light source set includes a circuit substrate, a battery and a light-emitting unit. The circuit substrate has a power source portion and a light source portion electrically connected to the power source portion. A connecting member and the battery are arranged at opposite sides of the power source portion. The light-emitting unit is arranged on the light source portion, and the distance between the light-emitting unit and the center axis of the optical route is greater than the radius of the objective lens unit. The battery activates the light-emitting unit to generate a light beam, and the light beam irradiates toward the center axis of the optical route.

Abstract: Techniques and examples of determination of receiver (RX) beam for radio link monitoring (RLM) based on available spatial quasi-co-location (QCL) information in New Radio (NR) mobile communications are described. An apparatus receives downlink (DL) signaling from a network. The apparatus determines whether to extend an evaluation period of RLM based on a quasi-co-location (QCL) association provided in at least the DL signaling. The apparatus then executes extension of the evaluation period of the RLM, or not, based on a result of the determining.

Abstract: A submicron-sized Pickering miniemulsion system stabilized by carbon quantum dots solid nanoparticles for biphasic catalysis is disclosed, which breaks the existing limits for homogenization of the immiscible biphasic system and overcomes the issues for big size of solid particles-stabilized emulsion droplets. A method for producing the carbon quantum dot-based catalysts and a process of establishing the Pickering miniemulsion system for biphasic reaction with enhanced catalytic efficiency are also disclosed. The carbon quantum dot-stabilized Pickering miniemulsion features a pH-responsive behavior, with a reversible transition between the emulsification and demulsification, triggering the easy & facile product separation and emulsifier/catalyst recycling in one reaction vessel.

Abstract: An artificial cornea and an associated manufacturing method are disclosed. The artificial cornea has two sides, each of which has an associated microstructure. In an embodiment, microlines can be provided on an anterior side, and a posterior side can have micropores. Both the geometry of the microstructures and their dimensions can be customized for an individual patient. The geometry of the artificial cornea itself and its dimensions can also be customized as such. In addition, the lifetime of the artificial cornea can be significantly enhanced by adding co-polymer(s) into the hydrogel to strengthen its mechanical properties. Patient recovery can be aided by adding peptides into the artificial cornea surfaces to improve cell growth post-operation.

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.