Patents by Inventor Chang-Yu Lin

Chang-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240327614
    Abstract: A method for manufacturing a play-of-color article includes the steps of: (a) providing a first mixture that contains a solvent and a plurality of functionalized colloidal particles; (b) replacing the solvent of the first mixture with a polymer solution that contains polymers, thereby obtaining a second mixture; (c) adding an initiator to the second mixture to obtain a third mixture, followed by injecting the third mixture into a mold and disturbing the third mixture, so that the third mixture is formed with a pattern; (d) leaving the third mixture to stand, so as to allow the functionalized colloidal particles therein to self-assemble to form a crystalline arrangement, thereby obtaining a fourth mixture; and (e) subjecting the polymers in the fourth mixture to a cross-linking reaction, thereby obtaining the play-of-color article. A play-of-color article manufactured by the method, and a play-of-color product including the play-of-color article are also provided.
    Type: Application
    Filed: March 22, 2024
    Publication date: October 3, 2024
    Applicants: Taiwan Green Point Enterprises Co., Ltd., Jabil Circuit (Singapore) Pte. Ltd.
    Inventors: Yi-Chung Su, Chih-Wen Lin, Chin-Yen Chou, Jiun-Shiuan Hsu, Yen-Hao Lin, Chang-Yu Lin
  • Publication number: 20240319560
    Abstract: An operation method of electronic device, comprising providing a first panel, wherein the first panel comprises first substrate, first medium layer disposed on the first substrate, a first electrode layer disposed between the first substrate and the first medium layer, and a second electrode layer disposed between the first electrode layer and the first medium layer; providing a second panel overlapped with the first panel, providing an adhesive layer, wherein the first panel is attached to the second panel through the adhesive layer, and the first panel and the second panel present a mirror-symmetrical structure with the adhesive layer as the axis of symmetry; applying a first voltage to the first electrode layer; applying a second voltage to the second electrode layer; applying a third voltage to the first electrode layer.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Innolux Corporation
    Inventors: Mei-Wen Jao, Chang-Chiang Cheng, Yung-Hsun Wu, Rui-An Yu, Yi-Hsin Lin
  • Patent number: 12100697
    Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first electronic device and a second electronic device. The first electronic device has an active surface and a lateral surface angled with the active surface, and the lateral surface includes a first portion and a second portion that is non-coplanar with the first portion. The second electronic device is disposed on the active surface of the first electronic device.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: September 24, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Cheng-Hsuan Wu
  • Patent number: 12068303
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 12045148
    Abstract: A verification system of a basic input output system and a verification method thereof are provided. The verification system includes a server, a microcontroller, and a verification device. The server includes a platform controller hub and the basic input output system. The server outputs a log file of the basic input output system by a system management bus controller in the platform controller hub. The microcontroller is coupled to the server. The microcontroller receives the log file and converts the log file into a readable character. The verification device is coupled to the microcontroller. The verification device receives and displays the readable character.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: July 23, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Hung Lin, Chang-Yu Tu, Wen-Shyan Lai
  • Publication number: 20240113061
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Patent number: 11942585
    Abstract: An optoelectronic package structure and a method of manufacturing an optoelectronic package structure are provided. The optoelectronic package structure includes a photonic component. The photonic component has an electrical connection region, a blocking region and a region for accommodating a device. The blocking region is located between the electrical connection region and the region for accommodating a device.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: March 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Hsuan Wu, Chang-Yu Lin, Yu-Sheng Huang
  • Publication number: 20230403078
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 14, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Cheng-Yuan KUNG, Hung-Yi LIN
  • Patent number: 11837566
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: December 5, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Ju Lu, Chi-Han Chen, Chang-Yu Lin, Jr-Wei Lin, Chih-Pin Hung
  • Patent number: 11722220
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Cheng-Yuan Kung, Hung-Yi Lin
  • Publication number: 20230006114
    Abstract: An optoelectronic package structure and a method of manufacturing an optoelectronic package structure are provided. The optoelectronic package structure includes a photonic component. The photonic component has an electrical connection region, a blocking region and a region for accommodating a device. The blocking region is located between the electrical connection region and the region for accommodating a device.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 5, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Hsuan WU, Chang-Yu LIN, Yu-Sheng HUANG
  • Publication number: 20220271019
    Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first electronic device and a second electronic device. The first electronic device has an active surface and a lateral surface angled with the active surface, and the lateral surface includes a first portion and a second portion that is non-coplanar with the first portion. The second electronic device is disposed on the active surface of the first electronic device.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Cheng-Hsuan WU
  • Patent number: 11296043
    Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chang-Yu Lin
  • Publication number: 20220084972
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Patent number: 11183474
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Ju Lu, Chi-Han Chen, Chang-Yu Lin, Jr-Wei Lin, Chih-Pin Hung
  • Publication number: 20210175189
    Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Chang-Yu LIN
  • Publication number: 20210167856
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Application
    Filed: January 8, 2021
    Publication date: June 3, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Cheng-Yuan KUNG, Hung-Yi LIN
  • Publication number: 20210167053
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 3, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Chi-Han CHEN, Chieh-Chen FU
  • Publication number: 20210134751
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Publication number: 20210126425
    Abstract: An optoelectronic package includes a substrate having a first surface and a second surface opposite to the first surface, an optoelectronic device on the first surface of the substrate, and a first conductive through via connecting the first surface and the second surface of the substrate. The optoelectronic device is electrically connected to the first conductive through via. A method for manufacturing the optoelectronic package is also provided.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Chi-Han CHEN, Pei-Jung YANG