Patents by Inventor Chang-Yu Lin

Chang-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145327
    Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.
    Type: Application
    Filed: December 27, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
  • Publication number: 20240128219
    Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 18, 2024
    Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
  • Publication number: 20240118528
    Abstract: A microscope device for observing a sample. The microscope device and the sample are located on an optical route. The microscope device includes an objective lens unit and an additional light source set. The light source set includes a circuit substrate, a battery and a light-emitting unit. The circuit substrate has a power source portion and a light source portion electrically connected to the power source portion. A connecting member and the battery are arranged at opposite sides of the power source portion. The light-emitting unit is arranged on the light source portion, and the distance between the light-emitting unit and the center axis of the optical route is greater than the radius of the objective lens unit. The battery activates the light-emitting unit to generate a light beam, and the light beam irradiates toward the center axis of the optical route.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 11, 2024
    Inventors: Chang-Ching YEH, Chang-Yu CHEN, Shu-Sheng LIN
  • Publication number: 20240113061
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Patent number: 11942585
    Abstract: An optoelectronic package structure and a method of manufacturing an optoelectronic package structure are provided. The optoelectronic package structure includes a photonic component. The photonic component has an electrical connection region, a blocking region and a region for accommodating a device. The blocking region is located between the electrical connection region and the region for accommodating a device.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: March 26, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Hsuan Wu, Chang-Yu Lin, Yu-Sheng Huang
  • Publication number: 20240088119
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20230403078
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 14, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Cheng-Yuan KUNG, Hung-Yi LIN
  • Patent number: 11837566
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: December 5, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Ju Lu, Chi-Han Chen, Chang-Yu Lin, Jr-Wei Lin, Chih-Pin Hung
  • Patent number: 11722220
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: August 8, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Cheng-Yuan Kung, Hung-Yi Lin
  • Publication number: 20230006114
    Abstract: An optoelectronic package structure and a method of manufacturing an optoelectronic package structure are provided. The optoelectronic package structure includes a photonic component. The photonic component has an electrical connection region, a blocking region and a region for accommodating a device. The blocking region is located between the electrical connection region and the region for accommodating a device.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 5, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Hsuan WU, Chang-Yu LIN, Yu-Sheng HUANG
  • Publication number: 20220271019
    Abstract: A semiconductor package structure and a method of manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first electronic device and a second electronic device. The first electronic device has an active surface and a lateral surface angled with the active surface, and the lateral surface includes a first portion and a second portion that is non-coplanar with the first portion. The second electronic device is disposed on the active surface of the first electronic device.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Cheng-Hsuan WU
  • Patent number: 11296043
    Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chang-Yu Lin
  • Publication number: 20220084972
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 17, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Patent number: 11183474
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Mei-Ju Lu, Chi-Han Chen, Chang-Yu Lin, Jr-Wei Lin, Chih-Pin Hung
  • Publication number: 20210175189
    Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Hung-Yi LIN, Chang-Yu LIN
  • Publication number: 20210167856
    Abstract: A system including optical devices is provided. The system includes a first substrate and a first device for optical communication. The first device has a first surface, a second surface opposite to the first surface, and a first side contiguous with the first surface and the second surface. Moreover, the first side is smaller than one of the first surface and the second surface in terms of area. The first device is attached at the first side thereof to the first substrate.
    Type: Application
    Filed: January 8, 2021
    Publication date: June 3, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Cheng-Yuan KUNG, Hung-Yi LIN
  • Publication number: 20210167053
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 3, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Chi-Han CHEN, Chieh-Chen FU
  • Publication number: 20210134751
    Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Mei-Ju LU, Chi-Han CHEN, Chang-Yu LIN, Jr-Wei LIN, Chih-Pin HUNG
  • Publication number: 20210126425
    Abstract: An optoelectronic package includes a substrate having a first surface and a second surface opposite to the first surface, an optoelectronic device on the first surface of the substrate, and a first conductive through via connecting the first surface and the second surface of the substrate. The optoelectronic device is electrically connected to the first conductive through via. A method for manufacturing the optoelectronic package is also provided.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Yu LIN, Chi-Han CHEN, Pei-Jung YANG
  • Patent number: 10930627
    Abstract: A semiconductor device package includes a first semiconductor device having a first surface, an interconnection element having a surface substantially coplanar with the first surface of the first semiconductor device, a first encapsulant encapsulating the first semiconductor device and the interconnection element, and a second semiconductor device disposed on and across the first semiconductor device and the interconnection element.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 23, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Yu Lin, Chi-Han Chen, Chieh-Chen Fu