Abstract: A transistor structure includes a substrate, a source electrode, a drain electrode, a protective layer and a gate electrode. The source electrode and the drain electrode are provided on the substrate. The protective layer is provided on the substrate. The protective layer is provided between the source electrode and the drain electrode. The protective layer includes a SiNx layer and a SiOx layer. The SiOx layer is provided on the substrate, the SiNx layer is provided on the SiOx layer, and a through hole of the protective layer is formed to extend through the SiNx layer and the SiOx layer. The gate electrode is provided in the through hole, and the gate electrode is separated from at least part of the SiOx layer so as to form an air gap therebetween.

Abstract: A verification system of a basic input output system and a verification method thereof are provided. The verification system includes a server, a microcontroller, and a verification device. The server includes a platform controller hub and the basic input output system. The server outputs a log file of the basic input output system by a system management bus controller in the platform controller hub. The microcontroller is coupled to the server. The microcontroller receives the log file and converts the log file into a readable character. The verification device is coupled to the microcontroller. The verification device receives and displays the readable character.

Abstract: An electronic apparatus installed with non-volatile memory express solid state disks (NVMe SSDs) is provided. The electronic apparatus includes a processor, a board management controller (BMC), a micro-controller, at least one first input and output (IO) expander, and a plurality of NVMe SSDs. The micro-controller is coupled to the processor and the BMC. The first IO expander is coupled between the micro-controller and the NVMe SSDs. The micro-controller reads a PRSNT # information and an IFDET # information of each of the NVMe SSDs through the first IO expander, and transmits the PRSNT # information and the IFDET # information of each of the NVMe SSDs to the processor and the BMC.

Abstract: A thermal simulation system adapted to establish a test environment for a thermal test is provided. The thermal simulation system includes a communication element, a controllable loading element, a plurality of connectors, and a controller. The communication element is configured to receive at least one of a heating control signal, a fan control signal, and a loading control signal from an external electronic device. The controllable loading element is configured to provide a loading. The connectors are configured to connect a heating element and a fan. The controller is configured to control a heat energy generated by the heating element according to the heating control signal, control a fan speed of the fan according to the fan control signal, and control a loading value of the loading provided by the controllable loading element according to the loading control signal.

Abstract: A hard drive disk indicator processing apparatus includes first and second processors. The first processor includes first, second and third communication interfaces. The first communication interface receives at least one serial general purpose input/output signal from a motherboard. The second communication interface receives a plurality piece of hard drive disk status information for responding to a plurality of hard drive disk statuses of hard drive disks. The third communication interface outputs serial information. The second processor includes fourth and fifth communication interfaces. The fourth communication interface is coupled to the third communication interface and receives the serial information. The fifth communication interface is coupled to a plurality of hard drive disk indicators. The first processor generates the serial information according to the at least one serial general purpose input/output signal.