Patents by Inventor Chang-Yun Chang

Chang-Yun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210202320
    Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.
    Type: Application
    Filed: December 17, 2020
    Publication date: July 1, 2021
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Keng-Yao Chen, Chen-Yu Tai, Yi-Ting Fu
  • Publication number: 20210193530
    Abstract: The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Keng-Yao CHEN, Chang-Yun CHANG, Ming-Chang WEN
  • Publication number: 20210183713
    Abstract: A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.
    Type: Application
    Filed: October 20, 2020
    Publication date: June 17, 2021
    Inventors: Chang-Jhih Syu, Chih-Hao Yu, Chang-Yun Chang, Hsiu-Hao Tsao, Yu-Jiun Peng
  • Publication number: 20210175126
    Abstract: A semiconductor device includes a substrate, first and second fins protruding from the substrate, and first and second source/drain (S/D) features over the first and second fins respectively. The semiconductor device further includes an isolation feature over the substrate and disposed between the first and second S/D features, and a dielectric layer disposed on sidewalls of the first and second S/D features and on sidewalls of the isolation feature. A top portion of the isolation feature extends above the dielectric layer.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
  • Patent number: 11031501
    Abstract: A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yun Chang, Ming-Ching Chang, Shu-Yuan Ku
  • Patent number: 10991628
    Abstract: A device includes a substrate; semiconductor fins extending from the substrate; an isolation structure over the substrate and laterally between the semiconductor fins; a liner layer between sidewalls of the semiconductor fins and the isolation structure; and an etch stop layer between the substrate and the isolation structure and laterally between the semiconductor fins. The etch stop layer includes a material different than that of the isolation structure and the liner layer.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Patent number: 10978351
    Abstract: A device that includes a substrate; semiconductor fins extending from the substrate; an isolation structure over the substrate and laterally between the semiconductor fins; a liner layer between sidewalls of the semiconductor fins and the isolation structure; and an etch stop layer between the substrate and the isolation structure and laterally between the semiconductor fins. The etch stop layer includes a material different than that of the isolation structure and the liner layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Patent number: 10930564
    Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
  • Patent number: 10868003
    Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
  • Publication number: 20200365465
    Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer lining the first trench; and forming a dielectric feature in the first trench.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yun CHANG, Bone-Fong WU, Ming-Chang WEN, Ya-Hsiu LIN
  • Patent number: 10741450
    Abstract: A method of forming a semiconductor device includes forming a gate structure over first and second fins over a substrate; forming an interlayer dielectric layer surrounding first and second fins; etching a first trench in the interlayer dielectric layer between the first and second fins uncovered by the gate structure; forming a helmet layer in the first trench; and filling the first trench with a dielectric feature.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yun Chang, Bone-Fong Wu, Ming-Chang Wen, Ya-Hsiu Lin
  • Publication number: 20200251325
    Abstract: A semiconductor structure includes a substrate, a pair of first fins extending from the substrate, a pair of second fins extending from the substrate, an isolation feature over the substrate and separating bottom portions of the first and the second fins, a pair of first epitaxial semiconductor features over the pair of first fins respectively, a pair of second epitaxial semiconductor features over the pair of second fins respectively, and a first dielectric feature sandwiched between and separating the pair of first epitaxial semiconductor features. The pair of second epitaxial semiconductor features merge with each other.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Publication number: 20200212217
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: December 24, 2019
    Publication date: July 2, 2020
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Patent number: 10651030
    Abstract: A semiconductor structure includes a substrate; first and second fins extending from the substrate and oriented lengthwise generally along a first direction; an isolation feature over the substrate and separating bottom portions of the first and the second fins; first and second epitaxial semiconductor features over the first and the second fins, respectively; and a first dielectric feature sandwiched between the first and the second epitaxial semiconductor features. A maximum width of the first dielectric feature is smaller than a width of the isolation feature between the first and the second fins along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Publication number: 20200119183
    Abstract: A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Chang-Yun Chang, Ming-Ching Chang, Shu-Yuan Ku
  • Publication number: 20200091008
    Abstract: A device includes a substrate; semiconductor fins extending from the substrate; an isolation structure over the substrate and laterally between the semiconductor fins; a liner layer between sidewalls of the semiconductor fins and the isolation structure; and an etch stop layer between the substrate and the isolation structure and laterally between the semiconductor fins. The etch stop layer includes a material different than that of the isolation structure and the liner layer.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Hung-Kai Chen
  • Publication number: 20200075421
    Abstract: A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.
    Type: Application
    Filed: August 9, 2019
    Publication date: March 5, 2020
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chang-Yun Chang, Ching-Feng Fu, Peng Wang
  • Patent number: 10573751
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Publication number: 20200058650
    Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
  • Publication number: 20200006354
    Abstract: SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region.
    Type: Application
    Filed: April 5, 2019
    Publication date: January 2, 2020
    Inventors: MING-CHANG WEN, KUO-HSIU HSU, JYUN-YU TIAN, WAN-YAO WU, CHANG-YUN CHANG, HUNG-KAI CHEN, LIEN JUNG HUNG