Patents by Inventor Chang-Yun Chang
Chang-Yun Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8110466Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.Type: GrantFiled: July 26, 2010Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Tsung-Lin Lee, Chang-Yun Chang
-
Publication number: 20120021589Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.Type: ApplicationFiled: September 29, 2011Publication date: January 26, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann
-
Publication number: 20120009690Abstract: The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleaning machine. The spectrometry machine receives a portion of the cleaning solution from the wafer-cleaning machine. The portion of the cleaning solution collects particles from the wafer during the cleaning. The spectrometry machine is operable to analyze a particle composition of a portion of the wafer based on the portion of the cleaning solution, while the wafer remains in the wafer-cleaning machine during the particle composition analysis.Type: ApplicationFiled: July 12, 2010Publication date: January 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Clement Hsingjen Wann, Hung-Ming Chen, Chang-Yun Chang, Sey-Ping Sun
-
Patent number: 8049300Abstract: An inductive device including an inductor coil located over a substrate, at least one electrically insulating layer interposing the inductor coil and the substrate, and a plurality of current interrupters each extending into the substrate, wherein a first aggregate outer boundary of the plurality of current interrupters substantially encompasses a second aggregate outer boundary of the inductor coil.Type: GrantFiled: June 25, 2007Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Andrew Yeh, Alex Chang, Sung-Pi Tseng, Chang-Yun Chang, Hao-Yu Chen, Fu-Liang Yang
-
Patent number: 8039179Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.Type: GrantFiled: December 29, 2010Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann
-
Publication number: 20110233679Abstract: An integrated circuit including a plurality of Fin field effect transistors (FINFETs) is provided. The integrated circuit includes a plurality of fin-channel bodies over a substrate. The fin-channel bodies include a first fin-channel body and a second fin-channel body. A gate structure is disposed over the fin-channel bodies. At least one first source/drain (S/D) region of a first FINFET is adjacent the first fin-channel body. At least one second source/drain (S/D) region of a second FINFET is adjacent the second fin-channel body. The at least one first S/D region is electrically coupled with the at least one second S/D region. The at least one first and second S/D regions are substantially free from including any fin structure.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Ming CHEN, Shao-Ming YU, Chang-Yun CHANG
-
Publication number: 20110212579Abstract: An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric.Type: ApplicationFiled: May 4, 2011Publication date: September 1, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yu Chen, Chang-Yun Chang, Di-Hong Lee, Fu-Liang Yang
-
Publication number: 20110195564Abstract: A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved.Type: ApplicationFiled: February 8, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jhon-Jhy Liaw, Chang-Yun Chang
-
Publication number: 20110175165Abstract: An angled implantation process is used in implanting semiconductor fins of a semiconductor device and provides for covering some but not necessarily all of semiconductor fins of a first type with patterned photoresist, and implanting using an implant angle such that all semiconductor fins of a second type are implanted and none of the semiconductor fins of the first type, are implanted. A higher tilt or implant angle is achieved due to the reduced portions of patterned photoresist, that are used.Type: ApplicationFiled: January 19, 2010Publication date: July 21, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Ming YU, Chang-Yun CHANG
-
Publication number: 20110156148Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Ming Yu, Chang-Yun Chang
-
Publication number: 20110151359Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality, of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.Type: ApplicationFiled: December 29, 2010Publication date: June 23, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann
-
Publication number: 20110133292Abstract: An integrated circuit structure includes a semiconductor substrate, and a FinFET over the semiconductor substrate. The FinFET includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin. A first pair of shallow trench isolation (STI) regions includes portions directly underlying portions of the source/drain regions, wherein the first pair of STI regions is separated by, and adjoining a semiconductor strip. The first pair of STI regions further has first top surfaces. A second pair of STI regions comprises portions directly underlying the gate electrode, wherein the second pair of STI regions is separated from each other by, and adjoining, the semiconductor strip. The second pair of STI regions has second top surfaces higher than the first top surfaces.Type: ApplicationFiled: July 26, 2010Publication date: June 9, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
-
Publication number: 20110121406Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.Type: ApplicationFiled: August 30, 2010Publication date: May 26, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Chih Cheih Yeh, Chang-Yun Chang, Feng Yuan
-
Publication number: 20110097889Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.Type: ApplicationFiled: July 26, 2010Publication date: April 28, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Yuan, Tsung-Lin Lee, Hung-Ming Chen, Chang-Yun Chang
-
Publication number: 20110097863Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.Type: ApplicationFiled: July 26, 2010Publication date: April 28, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Tsung-Lin Lee, Chang-Yun Chang
-
Publication number: 20110095372Abstract: An integrated circuit structure includes a substrate having a first portion in a first device region and a second portion in a second device region; and two insulation regions in the first device region and over the substrate. The two insulation regions include a first dielectric material having a first k value. A semiconductor strip is between and adjoining the two insulation regions, with a top portion of the semiconductor strip forming a semiconductor fin over top surfaces of the two insulation regions. An additional insulation region is in the second device region and over the substrate. The additional insulation region includes a second dielectric material having a second k value greater than the first k value.Type: ApplicationFiled: July 26, 2010Publication date: April 28, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Yuan, Tsung-Lin Lee, Hung-Ming Chen, Chang-Yun Chang
-
Publication number: 20110089526Abstract: A system and method for forming multi recessed shallow trench isolation structures on substrate of an integrated circuit is provided. An integrated circuit includes a substrate, at least two shallow trench isolation (STI) structures formed in the substrate, an oxide fill disposed in the at least two STI structures, and semiconductor devices disposed on the oxide fill in the at least two STI structures. A first STI structure is formed to a first depth and a second STI structure is formed to a second depth. The oxide fill fills the at least two STI structures, and the first depth and the second depth are based on semiconductor device characteristics of semiconductor devices disposed thereon.Type: ApplicationFiled: July 16, 2010Publication date: April 21, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Lee, Chang-Yun Chang
-
Publication number: 20110084340Abstract: An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions.Type: ApplicationFiled: November 4, 2009Publication date: April 14, 2011Inventors: Feng Yuan, Tsung-Lin Lee, Hung-Ming Chen, Chang-Yun Chang
-
Publication number: 20110068405Abstract: An exemplary structure for the fin field effect transistor comprises a substrate comprising a major surface; a plurality of fin structures protruding from the major surface of the substrate, wherein each fin structure comprises an upper portion and a lower portion separated at a transition location at where the sidewall of the fin structure is at an angle of 85 degrees to the major surface of the substrate, wherein the upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate and a top surface having a first width, wherein the lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width; and a plurality of isolation structures between the fin structures, wherein each isolation structure extends from the major surface of the substrate to a point above the transition location.Type: ApplicationFiled: April 23, 2010Publication date: March 24, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng YUAN, Hung-Ming CHEN, Tsung-Lin LEE, Chang-Yun CHANG, Clement Hsingjen WANN
-
Patent number: 7862962Abstract: Provided is a method including layout design of an integrated circuit. A first pattern is provided. The first pattern includes an array of dummy line features and a plurality of spacer elements abutting the dummy line features. A second pattern is provided. The second pattern defines an active region of an integrated circuit device. An edge spacer element of the active region is determined. A dummy line feature of the array of dummy line features is biased (e.g., increased in width), the dummy line feature is adjacent an edge spacer element.Type: GrantFiled: January 20, 2009Date of Patent: January 4, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann