Abstract: A semiconductor memory device is disclosed. The device can be controlled by a controller for another less integrated memory device. The device includes a set of a first memory cell array and a second memory cell array having word lines, a row decoding unit which simultaneously activates the first memory cell array and the second memory cell array, and pairs of input and output lines through which data transfer from and to the first memory cell array and the second memory cell array. The row decoding unit includes a decoder which decodes the row address, a first word line driver, and a second word line driver. The first word line driver, which connects to the power supply voltage, transmits the decoded row address to the first memory cell array so as to select the word lines corresponding to the row address among the word lines of the first memory cell array.