Abstract: A semiconductor die includes a substrate having a topside including active circuitry having an array of bond pads thereon separated by gaps including a minimum gap. At least a portion of the array of bond pads are connected to nodes in the active circuitry. At least one wire bond alignment sensing structure includes a first bond pad selected from the array of bond pads, and a guard element positioned along at least a portion of the first bond pad. The guard element is spaced apart by a distance shorter than the minimum gap from the first bond pad.

Abstract: A semiconductor die includes a substrate having a topside including active circuitry having an array of bond pads thereon separated by gaps including a minimum gap. At least a portion of the array of bond pads are connected to nodes in the active circuitry. At least one wire bond alignment sensing structure includes a first bond pad selected from the array of bond pads, and a guard element positioned along at least a portion of the first bond pad. The guard element is spaced apart by a distance shorter than the minimum gap from the first bond pad.

Abstract: In a semiconductor memory which comprises a main memory array, redundant memory cells, and a plurality of repair fuse boxes, a method of selecting redundant memory cells in relation to repair fuse boxes, comprising testing redundant memory cells to determine whether they are valid or defective, and making a selection of redundant memory cells which allocates valid redundant memory cells to respective repair fuse boxes but which does not allocate defective redundant memory cells to any repair fuse boxes.

Abstract: A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.

Abstract: A semiconductor integrated circuit memory device, and test method for a memory device are provided in which an external wordline voltage is applied to a wordline of the memory device. A current on the wordline is measured as a result of application of the externally supplied wordline voltage. The measured current is compared to a reference value to determine whether the wordline has a defect, in particular a short-circuit defect. A tester device is connected to the memory device and supplies the external wordline voltage. The current measurement and comparison may be made internally by circuitry on the memory device or externally by circuitry in a tester device.