Patents by Inventor Changge Qiao

Changge Qiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9003344
    Abstract: A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed. The preliminary routing information includes track assignment information. Timing-critical nets are identified based on statistical distribution of the preliminary routing information of the nets. The identified timing-critical nets are assigned to a set of routing layers and removed from future net pattern matching. The remaining nets are clustered into multiple net patterns based on their physical attributes. The scaling factor for each net pattern is updated based on the scaling factor standard deviation and net length of the net pattern. Nets that are outside multiple standard deviations of a net pattern are assigned to routing layers. The scaling factors of the net patterns and the layer assignments are applied to the next phase of placement-based optimizations.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: April 7, 2015
    Assignee: Synopsys, Inc.
    Inventors: Christopher Kennedy, Changge Qiao
  • Patent number: 8875075
    Abstract: A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, post-route information of nets in the circuit design is analyzed. The post-route information includes, for each of the nets, a predicted route property, a post-route property, and a set of physical and/or timing attributes for that net. For each of the attributes, a set of attribute ranges is derived for the corresponding attribute to bin the nets into a Gaussian distribution for that attribute. Net routing constraints are generated for the circuit design based on the attribute ranges derived. The net routing constraints are applied to one or more of the nets during subsequent placement-based optimizations of the circuit design.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: October 28, 2014
    Assignee: Synopsys, Inc.
    Inventors: Christopher Kennedy, Changge Qiao
  • Publication number: 20130346936
    Abstract: A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, post-route information of nets in the circuit design is analyzed. The post-route information includes, for each of the nets, a predicted route property, a post-route property, and a set of physical and/or timing attributes for that net. For each of the attributes, a set of attribute ranges is derived for the corresponding attribute to bin the nets into a Gaussian distribution for that attribute. Net routing constraints are generated for the circuit design based on the attribute ranges derived. The net routing constraints are applied to one or more of the nets during subsequent placement-based optimizations of the circuit design.
    Type: Application
    Filed: June 20, 2012
    Publication date: December 26, 2013
    Inventors: Christopher Kennedy, Changge Qiao
  • Publication number: 20130346937
    Abstract: A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed. The preliminary routing information includes track assignment information. Timing-critical nets are identified based on statistical distribution of the preliminary routing information of the nets. The identified timing-critical nets are assigned to a set of routing layers and removed from future net pattern matching. The remaining nets are clustered into multiple net patterns based on their physical attributes. The scaling factor for each net pattern is updated based on the scaling factor standard deviation and net length of the net pattern. Nets that are outside multiple standard deviations of a net pattern are assigned to routing layers. The scaling factors of the net patterns and the layer assignments are applied to the next phase of placement-based optimizations.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 26, 2013
    Inventors: Christopher Kennedy, Changge Qiao
  • Patent number: 8336015
    Abstract: A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual routing and lower-effort actual routing can be compared to identify nets having miscorrelation. Based on the nets having at least a predetermined miscorrelation, one or more patterns can be defined. At this point, net routing constraints and/or scaling factors can be assigned to nets matching the defined patterns. These net routing constraints and scaling factors can be applied to the nets of the design that match the patterns. Optimized placement and a higher-effort actual routing of the design can be performed using the nets with the applied net routing constraints and scaling factors. An optimized, routed design can be generated as output.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: December 18, 2012
    Assignee: Synopsys, Inc.
    Inventors: Changge Qiao, Chi-Min Chu, Jing C. Lin
  • Publication number: 20110061038
    Abstract: A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual routing and lower-effort actual routing can be compared to identify nets having miscorrelation. Based on the nets having at least a predetermined miscorrelation, one or more patterns can be defined. At this point, net routing constraints and/or scaling factors can be assigned to nets matching the defined patterns. These net routing constraints and scaling factors can be applied to the nets of the design that match the patterns. Optimized placement and a higher-effort actual routing of the design can be performed using the nets with the applied net routing constraints and scaling factors. An optimized, routed design can be generated as output.
    Type: Application
    Filed: January 29, 2010
    Publication date: March 10, 2011
    Applicant: Synopsys, Inc.
    Inventors: Changge Qiao, Chi-Min Chu, Jing C. Lin
  • Patent number: 7853915
    Abstract: A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 14, 2010
    Assignee: Synopsys, Inc.
    Inventors: Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, Jing C. Lin, Mahesh A. Iyer
  • Publication number: 20090319977
    Abstract: A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Applicant: Synopsys, Inc.
    Inventors: Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, Jing C. Lin, Mahesh A. Iyer