Abstract: The present disclosure relates to a system and apparatus for monitoring a partial discharge in a switchboard, including a plurality of partial discharge sensors provided in each of a plurality of switchboards to acquire partial discharge data generated in at least one switchboard, and a noise sensor provided in any one of the plurality of switchboards to acquire noise data to be differentiated from the partial discharge data acquired from the at least one partial discharge sensor, and it can be applied to other exemplary embodiments.

Abstract: A method for fabricating a semiconductor device includes: forming a first photoresist pattern with a first opening over an etch target layer; forming a second photoresist pattern with a plurality of second openings over the first photoresist pattern; and forming a plurality of patterns by etching the etch target layer by using the first photoresist pattern and the second photoresist pattern as an etch barrier.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.

Abstract: A method for fabricating a semiconductor device includes forming an interlayer dielectric layer over a substrate; forming a dual storage node contact plug to be buried in the interlayer dielectric layer, forming a first damascene pattern to isolate the dual storage node contact plug, forming a protective layer pattern inside the first damascene pattern, etching the interlayer dielectric layer to form a second damascene pattern to be coupled to the first damascene pattern, and forming bit lines inside the first and second damascene patterns.

Abstract: A method for fabricating a semiconductor device includes: forming a first photoresist pattern with a first opening over an etch target layer; forming a second photoresist pattern with a plurality of second openings over the first photoresist pattern; and forming a plurality of patterns by etching the etch target layer by using the first photoresist pattern and the second photoresist pattern as an etch barrier.

Abstract: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.

Abstract: A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.

Abstract: A method for fabricating a semiconductor device includes: forming a gate material over a substrate; etching the gate material to form gate patterns each including a portion of the gate material remaining over the substrate; performing a halo ion-implantation process on a portion of the substrate where a bit line contacts; forming sidewall spacers of the gate patterns; and etching the remaining portion of the gate material to expose the substrate using the sidewall spacers as a mask.

Abstract: Disclosed is a method for fabricating a cylinder type capacitor in a semiconductor device. Particularly, the cylinder type capacitor is fabricated through performing a series of processes. Among the serial processes, a cleaning process for removing a photosensitive layer remaining in undesired regions is performed before an etch-back process for forming bottom electrodes with use of the photosensitive layer as an etch mask. Especially, the cleaning process proceeds by employing one of a dry etching process and a wet etching process.

Abstract: Disclosed is a method for fabricating a cylinder type capacitor in a semiconductor device. Particularly, the cylinder type capacitor is fabricated through performing a series of processes. Among the serial processes, a cleaning process for removing a photosensitive layer remaining in undesired regions is performed before an etch-back process for forming bottom electrodes with use of the photosensitive layer as an etch mask. Especially, the cleaning process proceeds by employing one of a dry etching process and a wet etching process.