Patents by Inventor Changhoan Kim
Changhoan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11593167Abstract: Methods and systems for locking a cache line of a cache. A cache line is locked based on a count of a plurality of threads that access the cache line and maintained in the cache until all of the plurality of threads have loaded the cache line.Type: GrantFiled: May 9, 2019Date of Patent: February 28, 2023Assignee: International Business Machines CorporationInventors: Changhoan Kim, John A. Gunnels
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Patent number: 11288194Abstract: An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.Type: GrantFiled: December 12, 2018Date of Patent: March 29, 2022Assignee: International Business Machines CorporationInventors: Charles R. Johns, James A. Kahle, Martin Ohmacht, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Alessandro Morari, James C. Sexton, Patrick D. Siegl
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Patent number: 11288208Abstract: An approach is described that provides access to a named data element in a Coordination Namespace that is stored in a memory that is distributed amongst a set of nodes. A request of a name corresponding to the named data element is received from a requesting process and the approach responsively searches for the name in the Coordination Namespace. In response to determining an absence of data corresponding to the named data element, a pending state is indicated to the requesting process. In response to determining that the data corresponding to the named data element exists, a successful state is returned to the requesting process. In one embodiment, the successful state also includes providing the requesting process with access to the data corresponding to the named data element.Type: GrantFiled: December 12, 2018Date of Patent: March 29, 2022Assignee: International Business Machines CorporationInventors: Ravi Nair, Charles R. Johns, James A. Kahle, Changhoan Kim, Constantinos Evangelinos, Patrick D. Siegl
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Patent number: 11048758Abstract: A system for storing and looking up values via hash table is disclosed. The system comprises multiple hash tables, each hash table being associated with a different hashing function and a content addressable memory (CAM). One or more processors receive a request to store a value; generate hashes of the value via each of the hashing functions; determine whether there exists at least one hash table that has a vacancy for the value; and if the determination is positive, insert the value in one of the at least one hash tables having the vacancy, and if the determination is negative, insert the value in the CAM. The processors also receive a request to look up a value; determine whether any of the hash tables or the CAM contain the value; and return the determination of whether the any of the plurality of hash tables or the CAM contain the value.Type: GrantFiled: January 31, 2020Date of Patent: June 29, 2021Assignee: Morgan Stanley Services Group Inc.Inventors: Changhoan Kim, Sunghyun Park
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Patent number: 10915460Abstract: An approach is described that accesses data in a shared memory that is shared amongst nodes that include a local node and remote nodes. The local node receives a name corresponding to a named data element in a Coordination Namespace, the Coordination Namespace having been created in a memory distributed amongst the nodes. A hash function is applied to at least a portion of the name with a result of the hash function being a natural node indicator. Data corresponding to the named data element is requested from a natural node identified by the indicator. Based on the request, a response is received from the natural node.Type: GrantFiled: December 12, 2018Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Ravi Nair, Charles R. Johns, James A. Kahle, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Patrick D. Siegl
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Publication number: 20200356411Abstract: Methods and systems for locking a cache line of a cache. A cache line is locked based on a count of a plurality of threads that access the cache line and maintained in the cache until all of the plurality of threads have loaded the cache line.Type: ApplicationFiled: May 9, 2019Publication date: November 12, 2020Inventors: CHANGHOAN KIM, JOHN A. GUNNELS
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Publication number: 20200192820Abstract: An approach is described that provides access to a named data element in a Coordination Namespace that is stored in a memory that is distributed amongst a set of nodes. A request of a name corresponding to the named data element is received from a requesting process and the approach responsively searches for the name in the Coordination Namespace. In response to determining an absence of data corresponding to the named data element, a pending state is indicated to the requesting process. In response to determining that the data corresponding to the named data element exists, a successful state is returned to the requesting process. In one embodiment, the successful state also includes providing the requesting process with access to the data corresponding to the named data element.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Ravi Nair, Charles R. Johns, James A. Kahle, Changhoan Kim, Constantinos Evangelinos, Patrick D. Siegl
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Publication number: 20200192799Abstract: An approach is disclosed that maintains a consistent view of a virtual address by a local node which writes a first value to the virtual address and, after writing the first value, establishes a snapshot consistency state of the virtual address. The virtual address is shared amongst any number of processes and the processes includes a writing process and other processes that read from the virtual address. After writing the first value, the writing process writes a second value to the virtual address. Even after writing the second value, the first value is still visible to the other processes.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Charles R. Johns, James A. Kahle, Martin Ohmacht, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Alessandro Morari, James C. Sexton, Patrick D. Siegl
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Publication number: 20200192819Abstract: An approach is described that accesses data in a shared memory that is shared amongst nodes that include a local node and remote nodes. The local node receives a name corresponding to a named data element in a Coordination Namespace, the Coordination Namespace having been created in a memory distributed amongst the nodes. A hash function is applied to at least a portion of the name with a result of the hash function being a natural node indicator. Data corresponding to the named data element is requested from a natural node identified by the indicator. Based on the request, a response is received from the natural node.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Ravi Nair, Charles R. Johns, James A. Kahle, Changhoan Kim, Jose R. Brunheroto, Constantinos Evangelinos, Abdullah Kayi, Patrick D. Siegl
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Publication number: 20200050971Abstract: The disclosure is directed to optimizing parallel machine learning system design and performance using minibatch. A system for allocating data center resources according to embodiments includes: a machine learning process; a machine learning data set; a processing system including a P parallel processing elements for training the machine learning process using the machine learning data set, wherein the machine learning data set is split into a plurality of batches with a batch size M; and a resource manager for (1) minimizing a training time T=T(M,P) of the machine learning process over M for each value of P, and (2) efficient system design.Type: ApplicationFiled: August 8, 2018Publication date: February 13, 2020Inventors: Changhoan Kim, Michael P. Perrone
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Publication number: 20180341851Abstract: Optimizing the performance of a machine learning system includes: defining an n-dimensional approximate computing configuration space, the n-dimensional approximate computing configuration space defining tuning parameters for tuning the machine learning system; setting a performance objective for the machine learning system that identifies one or more machine learning system performance criteria; collecting and monitoring performance data; comparing the performance data to the machine learning system performance objective; and dynamically updating the n-dimensional approximate computing configuration space by adjusting the at least one tuning parameter, in response to the comparison.Type: ApplicationFiled: May 24, 2017Publication date: November 29, 2018Inventors: I-Hsin CHUNG, John A. GUNNELS, Changhoan KIM, Michael P. PERRONE, Bhuvana RAMABHADRAN
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Patent number: 9916163Abstract: A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.Type: GrantFiled: January 9, 2017Date of Patent: March 13, 2018Assignee: International Business Machines CorporationInventor: Changhoan Kim
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Patent number: 9870340Abstract: In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.Type: GrantFiled: March 30, 2015Date of Patent: January 16, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Constantinos Evangelinos, Changhoan Kim, Ravi Nair
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Publication number: 20170147347Abstract: A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.Type: ApplicationFiled: November 24, 2015Publication date: May 25, 2017Inventor: Changhoan Kim
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Publication number: 20170147352Abstract: A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.Type: ApplicationFiled: January 9, 2017Publication date: May 25, 2017Inventor: Changhoan Kim
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Patent number: 9652235Abstract: A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.Type: GrantFiled: November 24, 2015Date of Patent: May 16, 2017Assignee: International Business Machines CorporationInventor: Changhoan Kim
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Patent number: 9569215Abstract: A system for synchronizing parallel processing of a plurality of functional processing units (FPU), a first FPU and a first program counter to control timing of a first stream of program instructions issued to the first FPU by advancement of the first program counter; a second FPU and a second program counter to control timing of a second stream of program instructions issued to the second FPU by advancement of the second program counter, the first FPU is in communication with a second FPU to synchronize the issuance of a first stream of program instructions to the second stream of program instructions and the second FPU is in communication with the first FPU to synchronize the issuance of the second stream program instructions to the first stream of program instructions.Type: GrantFiled: August 15, 2016Date of Patent: February 14, 2017Assignee: International Business Machines CorporationInventor: Changhoan Kim
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Publication number: 20160292128Abstract: In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.Type: ApplicationFiled: March 30, 2015Publication date: October 6, 2016Inventors: Constantinos Evangelinos, Changhoan Kim, Ravi Nair
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Publication number: 20160291978Abstract: In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.Type: ApplicationFiled: March 10, 2016Publication date: October 6, 2016Inventors: Constantinos Evangelinos, Changhoan Kim, Ravi Nair
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Patent number: 8806141Abstract: A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.Type: GrantFiled: August 24, 2012Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Peter Boyle, Norman Christ, Alan Gara, Changhoan Kim, Robert Mawhinney, Martin Ohmacht, Krishnan Sugavanam