Patents by Inventor Chang-Hong Shen
Chang-Hong Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10600915Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.Type: GrantFiled: February 26, 2018Date of Patent: March 24, 2020Assignee: National Applied Research LaboratoriesInventors: Wen-Hsien Huang, Jia-Min Shieh, Chang-Hong Shen
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Publication number: 20180248044Abstract: A flexible substrate structure including a flexible substrate, a first dielectric layer, a metal-containing layer and a second dielectric layer is provided. The first dielectric layer is located on the flexible substrate. The metal-containing layer has a reflectivity greater than 15% and a heat transfer coefficient greater than 2 W/m-K. The metal-containing layer is disposed between the first dielectric layer and the second dielectric layer, and the second dielectric layer is an inorganic material layer. A flexible transistor including the above-mentioned flexible substrate structure and a method for fabricating the same are also provided.Type: ApplicationFiled: February 26, 2018Publication date: August 30, 2018Inventors: WEN-HSIEN HUANG, JIA-MIN SHIEH, CHANG-HONG SHEN
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Patent number: 9905547Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.Type: GrantFiled: October 14, 2015Date of Patent: February 27, 2018Assignee: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Chang-Hong Shen, Jia-Min Shieh, Wen-Hsien Huang, Tsung-Ta Wu, Chih-Chao Yang, Tung-Ying Hsieh
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Publication number: 20170110444Abstract: A chipset with light energy harvester, includes a substrate, a functional element layer, and a light energy harvesting layer, both are stacked vertically on the substrate, and an interconnects connected between the functional element layer and the light energy harvesting layer.Type: ApplicationFiled: October 14, 2015Publication date: April 20, 2017Inventors: CHANG-HONG SHEN, JIA-MIN SHIEH, WEN-HSIEN HUANG, TSUNG-TA WU, CHIH-CHAO YANG, TUNG-YING HSIEH
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Patent number: 9455350Abstract: A transistor device structure includes a substrate, a first polycrystalline semiconductor thin film and a first transistor unit. The first polycrystalline semiconductor thin film is disposed on the substrate. A grain diameter of the first polycrystalline semiconductor thin film is greater than 1 micrometer and a thickness of the first polycrystalline semiconductor thin film is less than three hundredths of the grain diameter. The first transistor unit is disposed on the first polycrystalline semiconductor thin film and includes a first gate dielectric layer and a first gate structure. The first gate dielectric layer is disposed on a surface of the first polycrystalline thin film semiconductor. The first gate structure is disposed on a surface of the first gate dielectric layer.Type: GrantFiled: March 25, 2014Date of Patent: September 27, 2016Assignee: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Jia-Min Shieh, Wen-Hsien Huang, Chang-Hong Shen, Chih-Chao Yang, Tung-Ying Hsieh
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Patent number: 9281305Abstract: A transistor device structure includes a substrate, a first transistor layer and a second transistor layer. The second transistor layer is disposed between the substrate and the first transistor layer. The first transistor layer includes an insulating structure and a first transistor unit. The insulating structure is disposed on the second transistor layer and has a protruding portion. The first transistor unit includes a gate structure, a source/drain structure, an embedded source/drain structure and a channel. The source/drain structure is disposed beside the gate structure and over the insulating structure. The embedded source/drain structure is disposed underneath the source/drain structure and in the insulating structure. The channel is defined between the protruding portion and the gate structure.Type: GrantFiled: December 5, 2014Date of Patent: March 8, 2016Assignee: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Chih-Chao Yang, Jia-Min Shieh, Wen-Hsien Huang, Tung-Ying Hsieh, Chang-Hong Shen, Szu-Hung Chen
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Publication number: 20150280010Abstract: A transistor device structure includes a substrate, a first polycrystalline semiconductor thin film and a first transistor unit. The first polycrystalline semiconductor thin film is disposed on the substrate. A grain diameter of the first polycrystalline semiconductor thin film is greater than 1 micrometer and a thickness of the first polycrystalline semiconductor thin film is less than three hundredths of the grain diameter. The first transistor unit is disposed on the first polycrystalline semiconductor thin film and includes a first gate dielectric layer and a first gate structure. The first gate dielectric layer is disposed on a surface of the first polycrystalline thin film semiconductor. The first gate structure is disposed on a surface of the first gate dielectric layer.Type: ApplicationFiled: March 25, 2014Publication date: October 1, 2015Applicant: National Applied Research LaboratoriesInventors: Jia-Min SHIEH, Wen-Hsien HUANG, Chang-Hong SHEN, Chih-Chao YANG, Tung-Ying HSIEH
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Patent number: 9040333Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.Type: GrantFiled: November 8, 2013Date of Patent: May 26, 2015Assignee: National Applied Research LaboratoriesInventors: Jia-Min Shieh, Chang-Hong Shen, Wen-Hsien Huang, Bau-Tong Dai, Jung Y. Huang, Hao-Chung Kuo
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Publication number: 20140264271Abstract: A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots.Type: ApplicationFiled: March 18, 2013Publication date: September 18, 2014Applicant: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Jia-Min Shieh, Wen-Hsien Huang, Yu-Chung Lien, Chang-Hong Shen, Fu-Ming Pan, Hao-Chung Kuo
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Publication number: 20140131716Abstract: A memory device comprises a substrate, a tunnel oxide layer, a charge trapping layer, a block oxide layer, a plurality of conductive quantum dots, a metal gate and a source/drain structure. The tunnel oxide layer is disposed on the substrate and has a thickness substantially less than or equal to 2 nm. The charge trapping layer is disposed on the tunnel oxide layer. The quantum dots are embedded in the charge trapping layer. The block oxide layer is disposed on the charge trapping layer. The metal gate essentially consisting of aluminum (Al), copper (Cu), tantalum nitride (TiN), titanium nitride (TaN), aluminum-silicon-copper (Al—Si—Cu) alloys or the arbitrary combinations thereof is disposed on the block oxide layer. The source/drain structure is disposed in the substrate.Type: ApplicationFiled: January 18, 2013Publication date: May 15, 2014Applicant: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Jia-Min Shieh, Yu-Chung Lien, Wen-Hsien Huang, Chang-Hong Shen, Min-Cheng Chen, Ci-Ling Pan
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Publication number: 20140065754Abstract: The invention discloses a method for fabricating power-generating module with solar cell. The method includes the steps of providing a flexible substrate; forming a solar cell unit on the flexible substrate by using a high density plasma at a temperature lower than about 150° C.; and forming a circuit unit on the flexible substrate; wherein the solar cell unit is coupled to the circuit unit, so as to provide the power needed for the operation of the circuit unit.Type: ApplicationFiled: November 8, 2013Publication date: March 6, 2014Applicant: NATIONAL APPLIED RESEARCH LABORATORIESInventors: Jia-Min SHIEH, Chang-Hong SHEN, Wen-Hsien HUANG, Bau-Tong DAI, Jung Y. HUANG, Hao-Chung KUO
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Publication number: 20120256181Abstract: The invention discloses a power-generating module with solar cell and method for fabricating the same. The power-generating module includes a flexible substrate, a circuit and a solar cell. Both of the circuit and the solar cell are formed on the flexible substrate and are connected with each other, such that the solar cell is capable of providing the power needed by the circuit for operation.Type: ApplicationFiled: June 10, 2011Publication date: October 11, 2012Inventors: Jia-Min SHIEH, Chang-Hong Shen, Wen-Hsien Huang, Bau-Tong Dai, Jung Y. Huang, Hao-Chung Kuo
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Patent number: 8216872Abstract: A light-trapping layer is integrated into a thin-film solar cell. It is integrated as a light-inlet layer, an intermediate layer or a shaded layer with nano-particles embedded in a transparent or non-transparent conductive film. Thus, light stays longer in an absorption layer with photocurrent increased; defects of interface between the absorption layer and the nano-material are decreased; anti-reflective effect to inlet light is enhanced; and a good integrity and a good reliability for long-time light-shining are obtained.Type: GrantFiled: February 21, 2011Date of Patent: July 10, 2012Assignee: National Applied Research LaboratoriesInventors: Jia-Min Shieh, Chang-Hong Shen, Wen-Hsien Huang, Shih-Chuan Wu, Bau-Tong Dai, Jung Y. Huang, Hao-Chung Kuo
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Patent number: 7888160Abstract: A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region.Type: GrantFiled: December 11, 2008Date of Patent: February 15, 2011Assignee: Mosel Vitelic Inc.Inventors: Chang Hong Shen, Pei Ting Lo
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Patent number: 7709823Abstract: The invention is directed to a group-III nitride vertical-rods substrate. The group-III vertical-rods substrate comprises a substrate, a buffer layer and a vertical rod layer. The buffer layer is located over the substrate. The vertical rod layer is located on the buffer layer and the vertical rod layer is comprised of a plurality of vertical rods standing on the buffer layer.Type: GrantFiled: October 25, 2006Date of Patent: May 4, 2010Assignees: Industrial Technology Research Institute, National Tsing Hua UniversityInventors: Chih-Ming Lai, Wen-Yueh Liu, Jenq-Dar Tsay, Jung-Tsung Hsu, Shang-Jr Gwo, Chang-Hong Shen, Hon-Way Lin
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Publication number: 20100015750Abstract: A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region.Type: ApplicationFiled: December 11, 2008Publication date: January 21, 2010Applicant: MOSEL VITELIC INC.Inventors: Chang Hong Shen, Pei Ting Lo
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Publication number: 20070272914Abstract: The invention is directed to a group-III nitride vertical-rods substrate. The group-III vertical-rods substrate comprises a substrate, a buffer layer and a vertical rod layer. The buffer layer is located over the substrate. The vertical rod layer is located on the buffer layer and the vertical rod layer is comprised of a plurality of vertical rods standing on the buffer layer.Type: ApplicationFiled: October 25, 2006Publication date: November 29, 2007Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL TSING HUA UNIVERSITYInventors: Chih-Ming Lai, Wen-Yueh Liu, Jenq-Dar Tsay, Jung-Tsung Hsu, Shang-Jr Gwo, Chang-Hong Shen, Hon-Way Lin