Abstract: The present disclosure provides an earphone charging case, which comprises a case body, a storage compartment, a lid body, and a transmission mechanism. The case body is provided with an accommodating cavity that has an opening at its upper end; the storage compartment is installed in the accommodating cavity in a manner configured to revolve up and down so as to have an upward exposure movement stroke in which the storage compartment swings toward the opening and a storing movement stroke in which the storage compartment goes down to move within the accommodating cavity; the lid body has an opening movement stroke for opening the opening and a closing movement stroke for closing the opening; and the transmission mechanism is in transmission connection with both the storage compartment and the lid body.

Abstract: Disclosed are an earcap structure and an earphone. The earcap structure includes an earcap body provided with an installation channel, the installation channel is sleeved on an outside of an in-ear body of an earphone, a cavity is provided in a wall of the installation channel, and the cavity is filled with a fluid filler to make the cavity squeezed and deformed in response to that an outside of the earcap body is in contact with a concha cavity.

Abstract: Disclosed is an earphone, including an earbud structure and an earphone handle; the earphone handle is rotatably connected to the earbud structure to adjust a wearing posture of the earphone handle. The main objective of the present application is to provide an earphone that can adjust the wearing posture of the earphone handle, thereby improving the user's wearing comfort.

Abstract: Embodiments of the disclosure provide for hierarchically distributed voltage regulation and power flow optimization in a power distribution network. According to one embodiment, a regional coordinator system may determine power flow for an autonomous grid (AG) representing a portion of the distribution network based on a set of voltage parameters from nodes in the AG. The set of voltage parameters my include a current voltage magnitude. The regional coordinator system may provide, to a central controller system of the distribution network, one or more power flow parameters based on the determined power flow for the AG.

Abstract: Embodiments of the disclosure provide for hierarchically distributed voltage regulation and power flow optimization in a power distribution network. According to one embodiment, a regional coordinator system may determine power flow for an autonomous grid (AG) representing a portion of the distribution network based ona set of voltage parameters from nodes in the AG. The set of voltage parameters my include a current voltage magnitude. The regional coordinator system may provide, to a central controller system of the distribution network, one or more power flow parameters based on the determined power flow for the AG.

Abstract: Node controllers in power distribution networks in accordance with embodiments of the invention enable dynamic frequency control. One embodiment includes a node controller comprising a network interface a processor; and a memory containing a frequency control application; and a plurality of node operating parameters describing the operating parameters of a node, where the node is selected from a group consisting of at least one generator node in a power distribution network wherein the processor is configured by the frequency control application to calculate a plurality of updated node operating parameters using a distributed process to determine the updated node operating parameter using the node operating parameters, where the distributed process controls network frequency in the power distribution network; and adjust the node operating parameters.

Abstract: Embodiments of the present invention provide a storage apparatus, and a system and a method for executing access operations. The apparatus includes an interleaved bus, N memory groups, and K direct-connect bus groups, where K is less than or equal to N; the interleaved bus includes M master interfaces and S slave interfaces, where M is less than or equal to S, and each master interface among the M master interfaces is configured to receive continuous-addresses access operations; each memory group among the N memory groups includes S memories respectively connected to the S slave interfaces, where the interleaved bus is configured to decode and send the continuous-addresses access operations to at least one memory group among the N memory groups in an interleaved manner; and a first direct-connect bus group among the K direct-connect bus groups receives and sends the discrete-addresses access operations to at least one memory group.

Abstract: Node controllers in power distribution networks in accordance with embodiments of the invention enable dynamic frequency control. One embodiment includes a node controller comprising a network interface a processor; and a memory containing a frequency control application; and a plurality of node operating parameters describing the operating parameters of a node, where the node is selected from a group consisting of at least one generator node in a power distribution network wherein the processor is configured by the frequency control application to calculate a plurality of updated node operating parameters using a distributed process to determine the updated node operating parameter using the node operating parameters, where the distributed process controls network frequency in the power distribution network; and adjust the node operating parameters.

Abstract: Embodiments of the present invention provide a storage apparatus, and a system and a method for executing access operations. The apparatus includes an interleaved bus, N memory groups, and K direct-connect bus groups, where K is less than or equal to N; the interleaved bus includes M master interfaces and S slave interfaces, where M is less than or equal to S, and each master interface among the M master interfaces is configured to receive continuous-addresses access operations; each memory group among the N memory groups includes S memories respectively connected to the S slave interfaces, where the interleaved bus is configured to decode and send the continuous-addresses access operations to at least one memory group among the N memory groups in an interleaved manner; and a first direct-connect bus group among the K direct-connect bus groups receives and sends the discrete-addresses access operations to at least one memory group.