Abstract: A class-F power amplifier (PA) with a matching network is disclosed herein. The class-F PA comprises a first switch and a second switch operating in differential mode, with a second harmonic trap circuitry selectively terminating the drain terminals to ground at a second harmonic frequency. The second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. The PA further comprises a common mode trap and a matching network to reduce the imbalance of the drain terminal impedance between first harmonics and third harmonics.

Abstract: A class-F power amplifier (PA) with a matching network is disclosed herein. The class-F PA comprises a first switch and a second switch operating in differential mode, with a second harmonic trap circuitry selectively terminating the drain terminals to ground at a second harmonic frequency. The second harmonic trap circuitry comprises a plurality of lumped inductive and capacitive components. The PA further comprises a common mode trap and a matching network to reduce the imbalance of the drain terminal impedance between first harmonics and third harmonics.

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.

Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.