Abstract: An apparatus and method for detecting blood vessels under the skin using transmissive light sources are provided.

Abstract: A laser system according to an example of the present disclosure comprises: a supercontinuum laser that generates light with a visible wavelength; a wavelength selector comprising a filter whose angle is adjustable and configured to filter the wavelength of light incident from the supercontinuum laser to have a wavelength corresponding to the angle of the filter based on the angle of the filter; a compressor configured to compress the pulse width of light incident from the wavelength selector; and, a non-linear crystal configured to convert the wavelength of light incident from the compressor into an ultraviolet wavelength.

Abstract: A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.

Abstract: A memory module includes a plurality of memory devices. Each of the plurality of memory devices includes a plurality of data input/output pads, a plurality of on-die termination (ODT) circuits each including one or more resistors, a plurality of transceiver circuits each including one or more transmission drivers and one or more reception buffers, and a plurality of equalizer circuits each including one or more inductors. Each of the plurality of equalizer circuits is connected to one of the plurality of data input/output pads, one of the plurality of ODT circuits, and one of the plurality of transceiver circuits. Each of the one or more transmission drivers drives a node of one of the plurality of data input/output pads. Inductances of the one or more inductors have individual values which are based on a driver strength of each of the one or more transmission drivers.

Abstract: The present invention provides a light source apparatus and method for integrating diffused light with high efficiency using a collimating including an axicon lens, collimating it, tuning the wavelength of desired light, and passing it.

Abstract: A delay-locked loop includes a delay line and a duty correction block. The delay line includes receives an input clock signal and includes a cascade of delay cells for respectively generating a plurality of delayed input clock signals based on the input clock signal. The duty correction block is for correcting a duty ratio of the input clock signal based on a duty ratio of at least one clock signal from among the input clock signal and the plurality of delayed input clock signals in a first duty correction operation in which the duty ratio of the input clock signal is corrected, and correcting a duty ratio of an output clock signal based on the duty ratio of the output clock in a second duty correction operation in which the duty ratio of the output clock signal is corrected.

Abstract: A semiconductor memory device includes a delay lock loop (DLL) performing a locking operation at a wide frequency range and reducing current consumption. The semiconductor memory device includes a (DLL) having serially connected delay cells that receive and delay an external clock signal, wherein a predetermined number of delay cells of the serially connected delay cells that are to perform a delay operation are turned on in response to a threshold frequency recognition signal and first and second delay cell on signals, and for generating an internal clock signal; and a controller for generating the threshold frequency recognition signal and the first and second delay cell on signals, which reduce current consumption of each of the serially connected delay cells and increase a period of delay time thereof, if more delay cells are to be turned on when a delay cell indicating a threshold frequency is turned on.

Abstract: According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.

Abstract: A semiconductor memory device includes a delay lock loop (DLL) performing a locking operation at a wide frequency range and reducing current consumption. The semiconductor memory device includes a (DLL) having serially connected delay cells that receive and delay an external clock signal, wherein a predetermined number of delay cells of the serially connected delay cells that are to perform a delay operation are turned on in response to a threshold frequency recognition signal and first and second delay cell on signals, and for generating an internal clock signal; and a controller for generating the threshold frequency recognition signal and the first and second delay cell on signals, which reduce current consumption of each of the serially connected delay cells and increase a period of delay time thereof, if more delay cells are to be turned on when a delay cell indicating a threshold frequency is turned on.

Abstract: A delay-locked loop includes a delay line and a duty correction block. The delay line includes receives an input clock signal and includes a cascade of delay cells for respectively generating a plurality of delayed input clock signals based on the input clock signal. The duty correction block is for correcting a duty ratio of the input clock signal based on a duty ratio of at least one clock signal from among the input clock signal and the plurality of delayed input clock signals in a first duty correction operation in which the duty ratio of the input clock signal is corrected, and correcting a duty ratio of an output clock signal based on the duty ratio of the output clock in a second duty correction operation in which the duty ratio of the output clock signal is corrected.

Abstract: According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.

Abstract: In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory device comprises: a plurality of data input/output drivers; and a plurality of data input/output pads, each connected to a corresponding one of the plurality of data input/output drivers. A first subset of the data input/output pads are connected to respective data input/output pins of a package, and several or all of a remaining subset of the data input/output pads that are not connected to data input/output pins of the package are connected to power pins of the package.

Abstract: In a semiconductor memory device the power level of which is strengthened by using data input/output pads in a no connection state, and a method of strengthening the power of the semiconductor memory device at a stabilized power level, the semiconductor memory device comprises: a plurality of data input/output drivers; and a plurality of data input/output pads, each connected to a corresponding one of the plurality of data input/output drivers. A first subset of the data input/output pads are connected to respective data input/output pins of a package, and several or all of a remaining subset of the data input/output pads that are not connected to data input/output pins of the package are connected to power pins of the package.