Patents by Inventor Chang Kyo LEE
Chang Kyo LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136531Abstract: A conductive composite material, a method of preparing the same, and a secondary battery including the same. The conductive composite material may increase the proportion of an active material when forming an electrode by chemically bonding a conductive material and a binder to each other. A method of preparing the conductive composite material comprises ionizing carbon-based particles in a predetermined polarity, ionizing PTFE particles in a polarity different from that of the carbon-based particles, and chemically bonding the ionized carbon-based particles and the ionized PTFE particles, which are ionized in different polarities, to each other.Type: ApplicationFiled: September 20, 2023Publication date: April 25, 2024Inventors: Seung Min Oh, Sung Ho Ban, Sang Hun Lee, Ko Eun Kim, Yoon Sung Lee, Chang Hoon Song, Hyeong Jun Choi, Jun Myoung Sheem, Jin Kyo Koo, Young Jun Kim
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Patent number: 11967492Abstract: The present disclosure relates to a thin film manufacturing apparatus including a chamber having an inner process space of a substrate, a substrate support unit connected to the chamber to support the substrate in the chamber, a heat source unit connected to the chamber and disposed opposite to the substrate support unit, a plasma generation unit connected to one side of the chamber to supply radicals between the substrate support unit and the heat source unit, and a baffle connected to the chamber and including a movement passage of the radicals therein and a plurality of first exhaust holes communicating with the movement passage, which are formed in a top surface thereof. The thin film manufacturing apparatus may improve uniformity of the thin film formed on the substrate.Type: GrantFiled: October 6, 2021Date of Patent: April 23, 2024Assignee: AP SYSTEMS INC.Inventors: Byoung Il Lee, Chang Kyo Kim, Chang Min Kwon, Seung Won Yu
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Publication number: 20230317138Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: June 7, 2023Publication date: October 5, 2023Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
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Patent number: 11749337Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: June 16, 2022Date of Patent: September 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Patent number: 11749338Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: July 29, 2022Date of Patent: September 5, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Publication number: 20230274776Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: May 9, 2023Publication date: August 31, 2023Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
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Publication number: 20220383931Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
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Patent number: 11475930Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: GrantFiled: January 5, 2021Date of Patent: October 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
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Publication number: 20220310151Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: June 16, 2022Publication date: September 29, 2022Inventors: Dae-Sik MOON, Gil-Hoon CHA, Ki-Seonk OH, Chang-Kyo LEE, Yeon-Kyu CHOI, Jung-Hwan CHOI, Kyung-Soo HA, Seok-Hun HYUN
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Patent number: 11423971Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: December 29, 2021Date of Patent: August 23, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Patent number: 11393522Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: January 14, 2021Date of Patent: July 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Publication number: 20220122648Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: December 29, 2021Publication date: April 21, 2022Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
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Publication number: 20220093144Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.Type: ApplicationFiled: December 1, 2021Publication date: March 24, 2022Inventors: DAE-SIK MOON, KYUNG-SOO HA, YOUNG-SOO SOHN, KI-SEOK OH, CHANG-KYO LEE, JIN-HOON JANG, YEON-KYU CHOI, SEOK-HUN HYUN
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Patent number: 11249662Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.Type: GrantFiled: June 29, 2020Date of Patent: February 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Wang-Soo Kim, Jung-Hwan Choi, Ki-Duk Park, Yoo-Chang Sung, Jin-Sung Youn, Chang-Kyo Lee, Ju-Ho Jeon, Jin-Seok Heo
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Patent number: 11211102Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.Type: GrantFiled: November 25, 2020Date of Patent: December 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Kyung-Soo Ha, Young-Soo Sohn, Ki-Seok Oh, Chang-Kyo Lee, Jin-Hoon Jang, Yeon-Kyu Choi, Seok-Hun Hyun
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Publication number: 20210233575Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: ApplicationFiled: January 5, 2021Publication date: July 29, 2021Inventors: YOUNG-HOON SON, SI-HONG KIM, CHANG-KYO LEE, JUNG-HWAN CHOI, KYUNG-SOO HA
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Publication number: 20210166749Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: ApplicationFiled: January 14, 2021Publication date: June 3, 2021Inventors: DAE-SIK MOON, GIL-HOON CHA, KI-SEOK OH, CHANG-KYO LEE, YEON-KYU CHOI, JUNG-HWAN CHOI, KYUNG-SOO HA, SEOK-HUN HYUN
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Publication number: 20210082479Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.Type: ApplicationFiled: November 25, 2020Publication date: March 18, 2021Inventors: DAE-SIK MOON, KYUNG-SOO HA, YOUNG-SOO SOHN, KI-SEOK OH, CHANG-KYO LEE, JIN-HOON JANG, YEON-KYU CHOI, SEOK-HUN HYUN
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Patent number: 10923175Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.Type: GrantFiled: December 21, 2018Date of Patent: February 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Sik Moon, Gil-Hoon Cha, Ki-Seok Oh, Chang-Kyo Lee, Yeon-Kyu Choi, Jung-Hwan Choi, Kyung-Soo Ha, Seok-Hun Hyun
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Patent number: 10916279Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: GrantFiled: April 14, 2020Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha