Patents by Inventor Changlong Huo

Changlong Huo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8754442
    Abstract: A silicon on insulator N type semiconductor device, includes a N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer; and an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: June 17, 2014
    Assignee: Southeast University
    Inventors: Longxing Shi, Qinsong Qian, Changlong Huo, Weifeng Sun, Shengli Lu
  • Publication number: 20130153956
    Abstract: A silicon on insulator integrated high-current N type combined semiconductor device, which can improve the current density, comprises a P type substrate and a buried oxide layer arranged thereon. A P type epitaxial layer divided into a region I and a region II is arranged on the buried oxide layer. The region I comprises an N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and agate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer. The region II comprises an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer are arranged on a silicon surface, and a polysilicon lattice is arranged on the gate oxide layer.
    Type: Application
    Filed: July 11, 2011
    Publication date: June 20, 2013
    Applicant: SOUTHEAST UNIVERSITY
    Inventors: Longxing Shi, Qinsong Qian, Changlong Huo, Weifeng Sun, Shengli Lu