Patents by Inventor Chang Min Kwak

Chang Min Kwak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240124666
    Abstract: A polyimide precursor monomer having an E value of 2.0 or more calculated by Equation 1 is selected among polyimide raw materials. A polyimide includes a structural unit derived from the polyimide precursor monomer having the E value of 2.0 or more. Optical properties of a polyimide film formed from the polyimide can be improved, and the optical properties of a polyimide film can be predicted from the E value of the polyimide precursor monomer even before production of the polyimide film.
    Type: Application
    Filed: September 19, 2023
    Publication date: April 18, 2024
    Inventors: Chang Q LEE, Hyo Shin KWAK, Cheol Min YUN, Seung Min JEON, Hyun Kyu CHO
  • Patent number: 11501149
    Abstract: A memory device comprising: N cell array regions, a computation processing block suitable for generating computation-completion data by performing a network-level operation on input data, the network-level operation indicating an operation of repeating a layer-level operation M times in a loop, the layer-level operation indicating an operation of performing N neural network computations in parallel, a data operation block suitable for storing the input data and (M*N) pieces of neural network processing information in the N cell array regions, and outputting the computation-completion data through the data transfer buffer, and an operation control block suitable for controlling the computation processing block and the data operation block.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Chang-Min Kwak
  • Patent number: 11243716
    Abstract: A memory system which includes a memory pool having a plurality of memory units and a controller suitable for controlling the plurality of memory units, wherein the controller includes a translation unit suitable for translating a system address into a local address within the memory pool, a threshold decision unit suitable for dynamically changing a threshold based on an a number of accesses to each local address for data within the memory pool, a data attribute determination unit suitable for determining an attribute of data associated with the translated local address based on the threshold and the number of accesses to the translated local address, and a data input/output unit suitable for controlling a memory unit associated with a new local address among the plurality memory units based on the attribute of the data.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Chang-Min Kwak
  • Publication number: 20210150318
    Abstract: A memory device comprising: N cell array regions, a computation processing block suitable for generating computation-completion data by performing a network-level operation on input data, the network-level operation indicating an operation of repeating a layer-level operation M times in a loop, the layer-level operation indicating an operation of performing N neural network computations in parallel, a data operation block suitable for storing the input data and (M*N) pieces of neural network processing information in the N cell array regions, and outputting the computation-completion data through the data transfer buffer, and an operation control block suitable for controlling the computation processing block and the data operation block.
    Type: Application
    Filed: May 6, 2020
    Publication date: May 20, 2021
    Inventor: Chang-Min KWAK
  • Patent number: 10733094
    Abstract: In accordance with an embodiment, a controller may be provided. The controller may include a selection block configured to select cold data among write data. The controller may include a compression block configured to generate a plurality of unit data by dividing the cold data according to a predetermined size, assign each of the unit data to each of a plurality of channels, and compressing in parallel each of the unit data to generate compressed data. The controller may include an arbitration block configured to generate a plurality of packet data by packetizing each of the compressed data, and outputting the packet data.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Chang-Min Kwak
  • Publication number: 20200201573
    Abstract: A memory system which includes a memory pool having a plurality of memory units and a controller suitable for controlling the plurality of memory units, wherein the controller includes a translation unit suitable for translating a system address into a local address within the memory pool, a threshold decision unit suitable for dynamically changing a threshold based on an a number of accesses to each local address for data within the memory pool, a data attribute determination unit suitable for determining an attribute of data associated with the translated local address based on the threshold and the number of accesses to the translated local address, and a data input/output unit suitable for controlling a memory unit associated with a new local address among the plurality memory units based on the attribute of the data.
    Type: Application
    Filed: September 16, 2019
    Publication date: June 25, 2020
    Inventor: Chang-Min KWAK
  • Publication number: 20190138439
    Abstract: In accordance with an embodiment, a controller may be provided. The controller may include a selection block configured to select cold data among write data. The controller may include a compression block configured to generate a plurality of unit data by dividing the cold data according to a predetermined size, assign each of the unit data to each of a plurality of channels, and compressing in parallel each of the unit data to generate compressed data. The controller may include an arbitration block configured to generate a plurality of packet data by packetizing each of the compressed data, and outputting the packet data.
    Type: Application
    Filed: June 14, 2018
    Publication date: May 9, 2019
    Applicant: SK hynix Inc.
    Inventor: Chang-Min KWAK
  • Publication number: 20040086260
    Abstract: Disclosed is a method for registering an identifier, which can stably and effectively perform a broadcasting channel management by registering a user's photo image in a memory of a digital video device as an identifier. To this end, the method comprises the steps of: recording an image in a storing unit of a digital video device as an identifier; and managing channels of the digital video device on the basis of the image identifier.
    Type: Application
    Filed: August 25, 2003
    Publication date: May 6, 2004
    Inventor: Chang-Min Kwak
  • Patent number: 6269121
    Abstract: In an apparatus for performing a motion estimation (ME) on a block (BL) within a current frame based on a predetermined reference frame (PRF), a difference block (DB) forming channel provides a DB representing a difference between the block and a corresponding reference BL. And a ME path deciding circuit provides a zero vector if AV≦TH1, AV being an activity value of the DB, provides the BL as a first BL if TH1<AV≦TH2 and divides the BL into sub BL's (SB's) if AV>TH2 and then provides the SB's as a set of second BL's (SBL's) if TH2<AV≦TH3 and the SB's as a set of third BL's (TBL's) if AV>TH3, wherein TH1, TH2 and TH3 are preset thresholds, respectively. A first ME circuit performs a ME on a sample BL obtained by subsampling the first BL within a first predetermined search region (PSR) in a sample reference frame by using a first block matching method (BMM) employing a predetermined full search technique (PFST) to generate a first MV.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: July 31, 2001
    Assignee: Daewoo Electronics Co., Ltd.
    Inventor: Chang Min Kwak
  • Patent number: 6128341
    Abstract: In an apparatus for performing motion estimation (ME) on a block of N.times.M pixels in a current frame based on a predetermined reference frame (RF), a block divider divides the block into subblocks (SB's) of K.times.L pixels and then classifies the SB's into A-group SB's and B-group SB's in accordance with the rule that all of the SB's in a same group be diagonally adjacent to each other. A first and a second decision circuits decide pixels satisfying a first and a second predetermined conditions among the pixels in the ASB's as A-group representative pixels (ARP's) and in the BSB's as B-group representative pixels (BRP's), respectively, wherein the first predetermined condition is different from the second predetermined condition. A sample block generator combines the ARP's with the BRP's to generate a sample block. And then, RF subsampling circuit generates a sample RF (SRF) by subsampling the predetermined RF in accordance with the same subsampling method described above.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: October 3, 2000
    Assignee: Daewoo Electronics Co., Ltd.
    Inventor: Chang-Min Kwak