Abstract: The disclosure discloses a CMOS image sensor, which includes a plurality of image sensor units and a resistance-to-digital converting unit. Each image sensor unit includes a pixel unit and a resistive random access memory unit connected to the pixel unit, the pixel unit is configured to convert a received optical signal into an analog signal and the resistive random access memory unit is configured to convert the analog electrical signal into a resistance value. The resistance-to-digital converting unit is connected to the plurality of the image sensor units, and is configured to convert the resistance value into a digital signal. The resistive random access memory unit is adopted in the present disclosure to replace a transistor device and is configured to convert resistance information of the resistive random access memory unit into a digital signal and output. Thus, digital quantization of image information is completed.

Abstract: The disclosure discloses a CMOS image sensor, which includes a plurality of image sensor units and a resistance-to-digital converting unit. Each image sensor unit includes a pixel unit and a resistive random access memory unit connected to the pixel unit, the pixel unit is configured to convert a received optical signal into an analog signal and the resistive random access memory unit is configured to convert the analog electrical signal into a resistance value. The resistance-to-digital converting unit is connected to the plurality of the image sensor units, and is configured to convert the resistance value into a digital signal. The resistive random access memory unit is adopted in the present disclosure to replace a transistor device and is configured to convert resistance information of the resistive random access memory unit into a digital signal and output. Thus, digital quantization of image information is completed.

Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

Abstract: A full-frame image sensor system comprises at least a pair of readout circuits, at least a pair of channel selection circuits, and at least a pair of interface circuits arranged symmetrically with respect to a pixel array; the readout circuits are electrically connected to two sides of the pixel array respectively; the channel selection circuit and the readout circuit on a same side of the pixel array are electrically connected to each other. The interface circuit and the channel selection circuit on a same side of the pixel array are electrically connected to each other. As a result, the circuits on the two sides of the pixel array are substantially symmetrical, the center of the pixel array coincides with the center of the entire chip.

Abstract: A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate.

Abstract: A full-frame image sensor system comprises at least a pair of readout circuits, at least a pair of channel selection circuits, and at least a pair of interface circuits arranged symmetrically with respect to a pixel array; the readout circuits are electrically connected to two sides of the pixel array respectively; the channel selection circuit and the readout circuit on a same side of the pixel array are electrically connected to each other. The interface circuit and the channel selection circuit on a same side of the pixel array are electrically connected to each other. As a result, the circuits on the two sides of the pixel array are substantially symmetrical, the center of the pixel array coincides with the center of the entire chip.

Abstract: The present disclosure provides a global shutter CMOS pixel circuit and its image capturing method. The global shutter CMOS pixel circuit comprising a power supply unit, a pixel signal generating unit, a signal sampling and holding unit and a signal outputting unit. An output of the pixel signal generating unit is connected to an input of the signal sampling and holding unit. An output of the signal sampling and holding unit is connected to an input of the signal outputting unit. The output signal of the pixel and the photo-generated current are set to a logarithmic relationship, which effectively increases the signal dynamic range. Therefore, image signal transmission with high speed and high dynamic range can be achieved simultaneously. Furthermore, the pixels in the present disclosure can eliminate the process variations, which increases the consistency of the pixels.

Abstract: A system and method for regulating transfer characteristics of an integral analog-to-digital converter are provided. The system comprises a cascade N-stage integrator structure having N integrators, the input end of the first integrator is connected to a voltage, the output end of each integrator is connected to the input end of the adjacent integrator, and the output end of the Nth integrator is connected to an output node (VRAMP). Wherein, the N is positive integer greater than or equal to 2. In the cascade multistage integrator structure, the voltage of the output node (VRAMP) is in direct proportion relation with the time to the power of N. By adopting a cascade multistage integrator according to the present disclosure, it is simple to regulate transfer characteristics of the ADC, and the cascade digital signal processing is convenient, which can reduce the ADC conversion time and improve the ADC conversion rate.